5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

Revision 12-06-06

SMSC COM20020I 3.3V

DATASHEET

4

Figure 14 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE.................................................51

Figure 15 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................52

Figure 16 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................53

Figure 17 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................54

Figure 18 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE .........................................55

Figure 19 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................56

Figure 20 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE .......................................57

Figure 21 – NORMAL MODE TRANSMIT OR RECEIVE TIMING ...............................................................................58

Figure 22 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING .........................................................................58

Figure 23 – TTL INPUT TIMING ON XTAL1 PIN .........................................................................................................59

Figure 24 – RESET AND INTERRUPT TIMING...........................................................................................................59

Figure 25 - 28 PIN PLCC PACKAGE DIMENSIONS ...................................................................................................60

Figure 26 - 48 PIN TQFP PACKAGE OUTLINE...........................................................................................................61

Figure 27 - EFFECT OF THE EF BIT ON THE TA/RI BIT ...........................................................................................63

LIST OF TABLES

Table 1 - Typical Media ................................................................................................................................................23

Table 2 - Read Register Summary...............................................................................................................................24

Table 3 - Write Register Summary ...............................................................................................................................25

Table 4 - Status Register ..............................................................................................................................................28

Table 5 - Diagnostic Status Register.............................................................................................................................29

Table 6 - Command Register........................................................................................................................................30

Table 7 - Address Pointer High Register .......................................................................................................................31

Table 8 - Address Pointer Low Register........................................................................................................................31

Table 9 - Sub Address Register ...................................................................................................................................31

Table 10 - Configuration Register ................................................................................................................................31

Table 11 - Setup 1 Register ..........................................................................................................................................33

Table 12 - Setup 2 Register ..........................................................................................................................................34