Electronic Components Datasheet Search |
|
COM20020I3V-HD Datasheet(PDF) 4 Page - SMSC Corporation |
|
COM20020I3V-HD Datasheet(HTML) 4 Page - SMSC Corporation |
4 / 69 page 5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM SMSC COM20020I 3.3V Rev.E Page 4 Revision 09-11-06 DATASHEET LIST OF FIGURES Figure 1 - COM20020I 3V Operation ...........................................................................................................................10 Figure 2 - Multiplexed, 8051-Like Bus Interface With RS-485 Interface.......................................................................16 Figure 3 - Non-Multiplexed, 6801-Like Bus Interface With RS-485 Interface ...............................................................17 Figure 4 - High Speed Cpu Bus Timing - Intel CPU Mode ...........................................................................................18 Figure 5 - COM20020I 3V Network Using RS-485 Differential Transceivers..................................................................20 Figure 6 - Dipulse Waveform For Data Of 1-1-0...........................................................................................................20 Figure 7 - Internal Block Diagram.................................................................................................................................22 Figure 8 – Sequential Access Operation......................................................................................................................35 Figure 9 – Ram Buffer Packet Configuration................................................................................................................38 Figure 10 - Command Chaining Status Register Queue................................................................................................40 Figure 11 - Multiplexed Bus, 68xx-Like Control Signals; Read Cycle...........................................................................48 Figure 12 - Multiplexed Bus, 80xx-Like Control Signals; Read Cycle...........................................................................49 Figure 13 - Multiplexed Bus, 68xx-Like Control Signals; Write Cycle...........................................................................50 Figure 14 - Multiplexed Bus, 80xx-Like Control Signals; Write Cycle...........................................................................51 Figure 15 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle...................................................................52 Figure 16 - Non-Multiplexed Bus, 80xx-Like Control Signals; Read Cycle...................................................................53 Figure 17 - Non-Multiplexed Bus, 68xx-Like Control Signals; Read Cycle...................................................................54 Figure 18 - Non-Multiplexed Bus, 68xx-Like Control Signals; Read Cycle...................................................................55 Figure 19 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle ...................................................................56 Figure 20 - Non-Multiplexed Bus, 80xx-Like Control Signals; Write Cycle ...................................................................57 Figure 21 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle ...................................................................58 Figure 22 - Non-Multiplexed Bus, 68xx-Like Control Signals; Write Cycle ...................................................................59 Figure 23 – Normal Mode Transmit Or Receive Timing ...............................................................................................60 Figure 24 – Backplane Mode Transmit or Receive Timing...........................................................................................61 Figure 25 – TTL Input Timing On XTAL1 Pin ...............................................................................................................62 Figure 26 – Reset And Interrupt Timing .......................................................................................................................62 Figure 27 - 28 Pin PLCC Package Dimensions............................................................................................................63 Figure 28 - 48 Pin TQFP Package Outline ...................................................................................................................64 Figure 29 - Effect Of The EF Bit On The TA/RI Bit.......................................................................................................66 Figure 30 - Example Of Interface Circuit Diagram To ISA Bus ....................................................................................68 LIST OF TABLES Table 1 - Typical Media ................................................................................................................................................23 Table 2 - Read Register Summary...............................................................................................................................24 Table 3 - Write Register Summary ...............................................................................................................................25 Table 4 - STATUS REGISTER .....................................................................................................................................28 Table 5 - DIAGNOSTIC STATUS REGISTER ..............................................................................................................29 Table 6 - COMMAND REGISTER ................................................................................................................................30 Table 7 - Address Pointer High Register .......................................................................................................................30 Table 8 - Address Pointer Low Register........................................................................................................................31 Table 9 - SUB ADDRESS REGISTER .......................................................................................................................31 Table 10 - Configuration Register ................................................................................................................................31 Table 11 - SETUP 1 REGISTER ..................................................................................................................................33 Table 12 - SETUP 2 REGISTER ..................................................................................................................................34 |
Similar Part No. - COM20020I3V-HD |
|
Similar Description - COM20020I3V-HD |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |