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USB2005 Datasheet(PDF) 9 Page - SMSC Corporation |
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USB2005 Datasheet(HTML) 9 Page - SMSC Corporation |
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9 / 21 page  Chapter 4 Block Diagram Figure 4.1 USB2005 Block Diagram USB2.0 PHY ( Transciever ) FAST 8051 CPU CORE ATA-66 Interface Debug Serial 2 wire ( Data/Strobe) 2 pins MEM/IO Bus 29pins GPIO 7 pins Configuration and Control Clock Generation SIE ( Serial Interface Engine ) Program Memory/ IO Bus Interrupt Controller Latch phase 0 Latch phase 1 Latch phase 2 60MHz 32 Bit Future phase 3 Osc Address 64 Bytes EP0TX 64 Bytes EP0RX 64 Bytes EP1TX 64 Bytes EP1RX Auto address generators Data @ 32 bit 15MHz SIE Control Regs Address Address Address Address Address EP0RX_BC EP1RX_BC RAMRD_A/B EP0TX_BC RAMWR_A/B ATA/ATAPI Drive 32 bit 15MHz Data Buss CLOCKOUT 12 MHz OPTIONAL External PHY 512 Bytes EP2 TX/RX Buffer A 1.25KB SRAM 768 Byte Program/Scratchpad SRAM Clocked byPhase 0 Clock Clocked byPhase 1 Clock Clocked byPhase 2 Clock EP1TX_BC Address 512 Bytes EP2 TX/RX Buffer B 48KB ROM ROMEN |
Similar Part No. - USB2005_07 |
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Similar Description - USB2005_07 |
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