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HMP8154EVAL1 Datasheet(PDF) 7 Page - Intersil Corporation |
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HMP8154EVAL1 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 34 page  7 4343.4 November 4, 2005 Normal 16-Bit YCbCr, 16-Bit RGB, 24-Bit RGB Formats When 16-bit YCbCr, 16-bit RGB data, or 24-bit RGB format is selected without 2X upscaling or flicker filtering, the pixel data is latched on the rising edge of CLK2 while CLK is low. Overlay data is also latched on the rising edge of CLK2 while CLK is low. The pixel and overlay input timing is shown in Figures 3 - 5. As inputs, BLANK, HSYNC, and VSYNC are latched on the rising edge of CLK2 while CLK is low. As outputs, HSYNC, VSYNC, and BLANK are output following the rising edge of CLK2 while CLK is high. In these modes of operation, CLK is one-half the CLK2 frequency. FIGURE 1. PIXEL AND OVERLAY INPUT TIMING - NORMAL 8-BIT YCBCR FIGURE 2. PIXEL AND OVERLAY INPUT TIMING - 8-BIT YCBCR WITH 2X UPSCALING Cb 0Y 0 Cr 0 Y 1 Cb 2Y 2 CLK2 P8-P15 BLANK (INPUT) PIXEL 0 PIXEL 1 PIXEL 2 OL0-OL2, M1, M0 Y N PIXEL N BLANK (OUTPUT) CLK CLK2 Cb 0 Y 0 Cr 0 Y 1 Cb 2 Y 2 P8-P15 BLANK (INPUT) PIXEL 0 PIXEL 1 PIXEL 2 OL0-OL2, M1, M0 Y N PIXEL N BLANK (OUTPUT) HMP8154, HMP8156A |
Similar Part No. - HMP8154EVAL1 |
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Similar Description - HMP8154EVAL1 |
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