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MBM29LV160T-80PFTN Datasheet(PDF) 3 Page - SPANSION |
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MBM29LV160T-80PFTN Datasheet(HTML) 3 Page - SPANSION |
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3 / 58 page  MBM29LV160T-80/-90/-12/MBM29LV160B-80/-90/-12 2 (Continued) Any individual sector is typically erased and verified in 1.0 second. (If already preprogrammed.) The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. The MBM29LV160T/B is erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6, or the RY/BY output pin. Once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. The MBM29LV160T/B also has a hardware RESET pin. When this pin is driven low, execution of any Embedded Program Algorithm or Embedded Erase Algorithm is terminated. The internal state machine is then reset to the read mode. The RESET pin may be tied to the system reset circuitry. Therefore, if a system reset occurs during the Embedded Program Algorithm or Embedded Erase Algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address locations being programmed or erased. These locations need re-writing after the Reset. Resetting the device enables the system’s microprocessor to read the boot-up firmware from the Flash memory. Fujitsu’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The MBM29LV160T/B memory electrically erases all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one byte/word at a time using the EPROM programming mechanism of hot electron injection. s FEATURES • Single 3.0 V read, program and erase Minimizes system level power requirements • Compatible with JEDEC-standard commands Uses same software commands as E2PROMs • Compatible with JEDEC-standard world-wide pinouts 48-pin TSOP (1) (Package suffix: PFTN-Normal Bend Type, PFTR-Reversed Bend Type) 48-pin CSOP (Package suffix: PCV) 48-ball FBGA (Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance 80 ns maximum access time • Sector erase architecture One 8K word, two 4K words, one 16K word, and thirty-one 32K words sectors in word mode One 16K byte, two 8K bytes, one 32K byte, and thirty-one 64K bytes sectors in byte mode Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded programTM* Algorithms Automatically programs and verifies data at specified address •Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion (Continued) |
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