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HI5630EVAL1 Datasheet(PDF) 7 Page - Intersil Corporation |
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HI5630EVAL1 Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 13 page  7 Timing Waveforms NOTES: 4. SN: N-th sampling period. 5. HN: N-th holding period. 6. BM, N: M-th stage digital output corresponding to N-th sampled input. 7. DN: Final data output corresponding to N-th sampled input. FIGURE 1. HI5630 INTERNAL CIRCUIT TIMING FIGURE 2. HI5630 INPUT-TO OUTPUT TIMING DN - 4 DN - 3 DN - 1 DN DN + 1 DN + 2 ANALOG INPUT CLOCK INPUT INPUT S/H 1ST STAGE 2ND STAGE 6TH STAGE DATA OUTPUT SN - 1 HN - 1 SN HN SN + 1 HN + 1 SN + 2 SN + 5 HN + 5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8 B1, N - 1 B1, N B1, N + 1 B1, N + 4 B1, N + 5 B1, N + 6 B1, N + 7 B2, N - 2 B2, N - 1 B2, N B2, N + 4 B2, N + 5 B2, N + 6 B9, N - 5 B9, N - 4 B9, N B9, N + 1 B9, N + 2 B9, N + 3 tLAT tOD tH DATA N-1 DATA N CLOCK INPUT DATA OUTPUT 1.5V tAP ANALOG INPUT tAJ 1.5V 2.4V 0.5V HI5630 |
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