© 2004 Fairchild Semiconductor Corporation

DS500171

www.fairchildsemi.com

August 1998

Revised October 2004

74VCXR162601

Low Voltage 18-Bit Universal Bus Transceivers

with 3.6V Tolerant Inputs and

Outputs and 26

Ω Series Resistors in the Outputs

General Description

The VCXR162601, 18-bit universal bus transceiver, com-

bines D-type latches and D-type flip-flops to allow data flow

in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable

(OEAB and OEBA), latch-enable (LEAB and LEBA), and

clock (CLKAB and CLKBA) inputs. The clock can be con-

trolled by the clock-enable (CLKENAB and CLKENBA)

inputs. For A-to-B data flow, the device operates in the

transparent mode when LEAB is HIGH. When LEAB is

LOW, the A data is latched if CLKAB is held at a HIGH-to-

LOW logic level. If LEAB is LOW, the A bus data is stored

in the latch/flip-flop on the LOW-to-HIGH transition of

CLKAB. Output-enable OEAB is active-LOW. When OEAB

is HIGH, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B but uses

OEBA, LEBA, CLKBA and CLKENBA.

The 74VCXR162601 is designed for low voltage (1.4V to

The VCXR162601 is also designed with 26

Ω series resis-

tors on both the A and B Port outputs. This design reduces

line noise in applications such as memory address drivers,

clock drivers, and bus transceivers/transmitters.

Features

s 3.6V tolerant inputs and outputs

s 26

Ω series resistors on both the A and B Port outputs.

s Power-down HIGH impedance inputs and outputs

s Supports live insertion/withdrawal (Note 1)

±12 mA @ 3.0V V

CC

s Uses patented noise/EMI reduction circuitry

s Latchup performance exceeds 300 mA

s ESD performance:

Human body model

> 2000V

Machine model

>200V

Note 1: To ensure the high-impedance state during power up or power

value of the resistor is determined by the current-sourcing capability of the

driver.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Order Number

Package

Package Description

Number

74VCXR162601MTD

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide