Philips Semiconductors Linear Products

Product specification

NE5020

10-Bit

µP-compatible D/A converter

August 31, 1994

763

Figure 10.

NE5020

DIG GND (PIN 1)

+5V

PIN 1

IN4148

3.6k

Ω

3.6k

Ω

6.2k

Ω

+10V

PIN 1

0.1

µF

PIN 1

IN4148

2N3904

1.3k

Ω

3.9k

Ω

1k

Ω

IN4148

PIN 1

10k

Ω

–5V TO –10V

NOTE: DO NOT EXCEED NEGATIVE

LOGIC INPUT RANGE OF DAC

6.2V

ZENER

10k

Ω

9.1k

Ω

PIN 1

PIN 1

0.1

µF

6.2k

Ω

+12V TO +15V

+15V

10k ECL

VTH ≥ –1.29V

+10V CMOS

VTH = +9.0V

+5V CMOS

VTH = +2.8V

TTL,

DTL VTH = +1.4V

VTH = VPIN1 + 1.4V

+15V CMOS, HTL, HNIL

VTH = +7.6V

PMOS

VTH = 0V

CIRCUIT DESCRIPTION

The NE5020 provides ten data latches, an internal voltage

reference, application resistors, and a scaled output voltage in

addition to the basic DAC components (see Block Diagram).

Latch Circuit

Digital interface with the NE5020 is readily accomplished through

static- and threshold-sensitive. When the latch enable ports (LE)

are high (Logic ‘1’) the data inputs become very high impedances

and essentially disappear from the data bus. Addressing the LE

with a low static (Logic ‘0’), the latches become active and adapt the

logic states present on the data bus. During this state, the output of

the DAC will change to the value proportional to the data bus value.

When the latch enable returns to a high state, the selected set of

data inputs (i.e., depending on which LE goes high) ‘memorizes’ the

data bus logic states and the output changes to the unique output

value corresponding to the binary word in the latch.

The data inputs are inactive and high impedance (typically requiring

–2

µA for low (0.8V max) or 0.1µA for high (2.0V min) when the LE is

high. Any changes on the data bus with LE high will have no effect

on the DAC output.

The digital logic inputs (LE and DB) for the NE5020 utilize a

differential input logic system with a threshold level of +1.4V with

respect to the voltage level on the digital ground pin (Pin 1). Figure

10 details several bias schemes used to provide the proper

threshold voltage levels for various logic families.

To be compatible with a bus-oriented system, the DAC should

respond in as short a period as possible to insure full utilization of

the microprocessor, controller and I/O control lines. Figure 9 shows

the typical timing requirements of the latch and data lines. This

figure indicates that data on the data bus should be stable for at

least 50ns after LE is changed to a high state.

from an 8-bit bus (see Figure 11). Data for the two MSBs is supplied

remaining eight LSBs of data are transferred into the DAC. With

bus is complete.

Occasionally the analog output must change to its data value within

one data address operation. This is no problem using the NE5020

on a 16-bit bus or any other data bus with 10 or greater data bits.

This can be accomplished from an 8-bit data bus by utilizing an

external latch circuit to pre-load the two MSB data values. Figure 12

shows the circuit configuration.

After pre-loading (via LE pre-load) the external latch with the two

MSBs are concurrently loaded into the DAC in one address

operation. This permits the DAC output to make its appropriate

change at one time.