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NE5020F Datasheet(PDF) 9 Page - NXP Semiconductors |
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NE5020F Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 10 page Philips Semiconductors Linear Products Product specification NE5020 10-Bit µP-compatible D/A converter August 31, 1994 765 Figure 13. Bipolar Output DAC CURRENT FROM CURRENT SWITCHES OUTPUT AMP To R-2R Ladder DAC AMP BIPOLAR OFFSET (18) JUMPER FOR BIPOLAR OPERATION SUM NODE (22) (16) + – – + 5k 5k (17) VREF IN ID (ID IREF) VCC IREF 5k Reference Interface The NE5020 contains an internal bandgap voltage reference which is designed to have a very low temperature coefficient and excellent long-term stability characteristics. The internal bandgap reference (1.23V) is buffered and amplified to provide the 5V reference output. Providing a VREF ADJ (Pin 14) allows trimming of the reference output. Utilization of the adjust circuit shown in Figure 15 performs not only VREF adjustment, but also full-scale output adjust. Notice that the VREF ADJ pin is essentially the sum node of an op amp and is sensitive to excessive node capacitance. Any capacitance on the node can be minimized by placing the external resistors as close as possible to the VREF ADJ pin and observing good layout practices. The VREF OUT node can drive loads greater than the DAC VREF input requirements and can be used as an excellent system voltage reference. However, to minimize load effects on the DAC system accuracy, it is recommended that a buffer amplifier be used. Input Amplifier The DAC reference amplifier is a high gain internally-compensated op amp used to convert the input reference voltage to a precision bias current for the DAC ladder network. The Block Diagram details the input reference amplifier and current ladder. The voltage-to-current converter of the DAC amp will generate a 1mA reference current through QR with a 5V VREF. This current sets the input bias to the ladder network. Data bit 9 (DB9)(Q9), when turned on, will mirror this current and will contribute 1mA to the output. DB8 (Q8) will contribute 1/2 of that value or 0.5mA, and so on. These current values act as current sinks and will add at the sum node to produce a DAC ladder to sum node function of: I OUT + 2V REF R REF DB9 2 ) DB8 4 ) DB7 8 ) DB6 16 ) DB5 32 ) DB4 64 ) DB3 128 ) DB2 256 ) DB1 512 ) DB0 1024 Because of the fixed internal compensation of the reference amp, the slew rate is limited to typically 0.7V/ µs and source impedance at the VREF INPUT greater than 5kΩ should be avoided to maintain stability. The –VREF INPUT pin is uncommitted to allow utilization of negative polarity reference voltages. In this mode +VREF INPUT is grounded and the negative reference is tied directly to the –VREF INPUT contains a 5k Ω resistor that matches a like resistor in the +VREF INPUT to reduce voltage offset caused by op amp input bias currents. Output Amplifier and Interface The NE5020 provides an on-chip output op amp to eliminate the need for additional external active circuits. Its two-stage design with feed-forward compensation allows it to slew at 15V/ µs and settle to within ±1/2LSB in 5µs. These times are typical when driving the rated loads of RL ≥ 5k and CL 50pF with recommended values of CFF = 1nF and CFB = 30pF. Typical input offset voltages of 5mV and 50k Ω open-loop gain insure that an accurate current-to-voltage conversion is performed when using the on-chip RFB resistor. RFB is matched to RREF and RBIP to maintain accurate voltage gain over operating conditions. The diode shown from ground to sum node prevents the DAC current switches from saturating the op amp during large signal transitions which would otherwise increase the settling time. The output op amp also incorporates output short circuit protection for both positive and negative excursions. During this fault condition IOUT will limit at ±15mA typical. Recovery from this condition to rated accuracy will be determined by duration of short-circuit and die temperature stabilization. |
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