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ISL24011 Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL24011 Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 9 page 7 FN6196.2 March 28, 2006 Application Information General The ISL24011 is an octal voltage level shifter. The part was designed to level shift a digital input signal to +22V and -5V for TFT-LCD displays and is capable of level shifting input logic signals (0V to 5.5V) to outputs as large as +40V and -20V. Power Supply Decoupling The ISL24011 requires a 1.0µF decoupling capacitor as close to the VON1, VON2 and VOFF power supply pins, as possible, for a large load equal to 5k Ω in parallel with 4700pF (Figure 16). This will reduce any dv/dt between the different supplies and prevent the internal ESD clamp from turning on and damaging the part. For lighter loads such as a series 200 Ω resistor and a 3300pF capacitance, the decoupling capacitors can be reduced to 0.47µF. Power Supply Sequence The ISL24011 requires that VON2 be greater than or equal to VON1 at all times. Therefore, if VON1 and VON2 are different supplies, then VON2 needs to be turned on before VON1. The reason for this requirement is shown in Circuit 4 in the Pin Description Table. The ESD protection diode between VON2 and VON1 will forward bias if VON1 becomes a diode drop greater than VON2. Recommended power supply sequence: VON2, VON1, VOFF, then input logic signals. The ESD protection scheme is based on diodes from the pins to the VON2 supply and a dv/dt-triggered clamp. This dv/dt-triggered clamp imposes a maximum supply turn-on slew rate of 10V/µs. This clamp will trigger if the supply powers up too fast, causing amps of current to flow. Ground and VON1 are treated as I/O pins with this protection scheme. In applications where the dv/dt supply ramp could exceed 10V/µs, such as hot plugging, additional methods should be employed to ensure the rate of rise is not exceeded. Latch-up Proof The ISL24011 is manufactured in a high voltage DI process that isolates every transistor in its own tub making the part latch-up proof. Input Pin Connections Unused inputs must be tied to ground. Failure to tie unused input pins to ground will result in rail to rail oscillations on the respective output pins and higher unwanted power dissipation in the part. Under these conditions, the temperature of the part could get very hot. Limiting the Output Current No output short circuit current limit exists on this part. All applications need to limit the output current to less than 80mA. Adequate thermal heat sinking of the parts is also required. Application Diagram (TV) FIGURE 13. TRANSIENT RESPONSE vs LOAD CAPACITANCE Typical Performance Curves TA = 25°C, Output load parallel RC (RL = 5kΩ, CL = 4700pF) unless otherwise specified. (Continued) 0 0 400ns/DIV 1800pF 4700pF PULSE INPUT 50kHz 10% DUTY CYCLE VON1 & VON2 = 22V VOFF = -5V ISL24011 FIGURE 14. TYPICAL TV APPLICATION CIRCUIT 1.0µF 1.0µF DC/DC CONVERTER TIMING CONTROLLER LEVEL LCD PANEL 1.0µF VON1 VON2 VOFF SHIFTER ISL24011 |
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