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FAN5240MTC Datasheet(PDF) 10 Page - Fairchild Semiconductor |
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FAN5240MTC Datasheet(HTML) 10 Page - Fairchild Semiconductor |
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10 / 19 page  10 www.fairchildsemi.com FAN5240 Rev. 1.2.0 Current Processing Section The following discussion refers to Figure 6. Setting RSENSE Each phase current is sampled about 200nS after the SW node crosses 0V. For proper converter operation, choose an RSENSE value of: which is about 1K for the components in Figure 1. Active Droop The core converter incorporates a proprietary output voltage droop method for optimum handling of fast load transients found in modern processors. “Active droop” or voltage positioning is now widely used in the computer power applications. The technique is based on raising the converter voltage at light load in anticipation of a step increase in load current, and con- versely, lowering VCORE in anticipation of a step decrease in load current. With Active Droop, the output voltage varies with the load as if a resistor were connected in series with the con- verter’s output, in other words, it's effect is to raise the output resistance of the converter. Figure 5. Active Droop To get the most from the Active Droop, its magnitude should be scaled to match the output capacitor’s ESR voltage drop. Active Droop allows the size and cost of the output capacitors required to handle CPU current transients to be reduced. The reduction may be almost a factor of 2 when compared to a system without Active Droop. Figure 6. Current Limit and Active Droop Circuits R SENSE R DS ON () IMAX • 40 µA ----------------------------------------- = 1.2 I LOAD V DROOP I MAX V DROOP I MAX ESR × = (6) LDRV1 PGND1 ISNS1 in + in D 2.5V ILIM det. 1 R SENSE V to I ISNS1 5 ISNS1 8 I2 = ILIM ILIM 0.9V R ILIM ILIM mirror S/H ISNS2 5 To A1 (+) ISNS1 ISNS2 A B A-B B-A ISNS2-ISNS1 ISNS1-ISNS2 Σ |
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