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NE568A Datasheet(PDF) 1 Page - NXP Semiconductors

Part No. NE568A
Description  150MHz phase-locked loop
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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Philips Semiconductors
Product specification
NE/SA568A
150MHz phase-locked loop
1
1996 Feb 1
853-1558 16328
DESCRIPTION
The NE568A is a monolithic phase-locked loop (PLL) which
operates from 1Hz to frequencies in excess of 150MHz and features
an extended supply voltage range and a lower temperature
coefficient of the VCO center frequency in comparison with its
predecessor, the NE 568. The NE568A is function and
pin-compatible with the NE568, requiring only minor changes in
peripheral circuitry (see Figure 3). Temperature compensation
network is different, no resistor on Pin 12, needs to be grounded and
Pin 13 has a 3.9k
Ω resistor to ground. Timing cap, C2, is different
and for 70MHz operation with temperature compensation network
should be 16pF, not 34pF as was used in the NE568. The NE568A
has the following improvements: ESD protected; extended VCC
range from 4.5V to 5.5V; operating temperature range -55 to 125
°C
(see Signetics Military 568A data sheet); less layout sensitivity; and
lower TC of VCO (center frequency). The integrated circuit consists
of a limiting amplifier, a current-controlled oscillator (ICO), a phase
detector, a level shift circuit, V/I and I/V converters, an output buffer,
and bias circuitry with temperature and frequency compensating
characteristics. The design of the NE568A is particularly well-suited
for demodulation of FM signals with extremely large deviation in
systems which require a highly linear output. In satellite receiver
applications with a 70MHz IF, the NE568A will demodulate
±20%
deviations with less than 1.0% typical non-linearity. In addition to
high linearity, the circuit has a loop filter which can be configured
with series or shunt elements to optimize loop dynamic
performance. The NE568A is available in 20-pin dual in-line and
20-pin SO (surface mounted) plastic packages.
FEATURES
Operation to 150MHz
High linearity buffered output
PIN CONFIGURATION
VCC2
GND1
D, N Packages
LF1
VCC1
REFBYP
PNPBYP
INPBYP
LF3
LF2
LF4
FREQ ADJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
19
18
17
16
15
OUTFILT
VOUT
TCADJ2
VIN
TCADJ1
GND2
GND1
TCAP1
TCAP2
TOP VIEW
SR01037
Figure 1. Pin Configuration
Series or shunt loop filter component capability
External loop gain control
Temperature compensated
ESD protected1
APPLICATIONS
Satellite receivers
Fiber optic video links
VHF FSK demodulators
Clock Recovery
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
20-Pin Plastic Small Outline Large (SOL) Package
0 to +70
°C
NE568AD
SOT163-1
20-Pin Plastic Dual In-Line Package (DIP)
0 to +70
°C
NE568AN
SOT146-1
20-Pin Plastic Small Outline Large (SOL) Package
-40 to +85
°C
SA568AD
SOT163-1
20-Pin Plastic Dual In-Line Package (DIP)
-40 to +85
°C
SA568AN
SOT146-1
BLOCK DIAGRAM
PHASE
DETECTOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LEVEL SHIFT
V/I
CONVERTER
AMP
I/V
CONVERTER
OUT
BUF
LEVEL SHIFT
TCADJ
BIAS
ICO
VCC2
GND1
LF1
VCC1
REFBYP
PNPBYP
INPBYP
LF3
LF2
LF4
FREQ ADJ
OUTFILT
VOUT
TCADJ2
VIN
TCADJ1
GND2
GND1
TCAP1
TCAP2
NOTE:
Pins 4 and 5 can tolerate
1000V only, and all other
pins, greater than 2000V
for ESD (human body
model).
SR01038
Figure 2. Block Diagram




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