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NE568A Datasheet(PDF) 2 Page - NXP Semiconductors

Part No. NE568A
Description  150MHz phase-locked loop
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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Philips Semiconductors
Product specification
NE/SA568A
150MHz phase-locked loop
1996 Feb 1
2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
RATING
UNITS
VCC
Supply voltage
6
V
TJ
Junction temperature
+150
°C
TSTG
Storage temperature range
-65 to +150
°C
PDMAX
Maximum power dissipation
400
mW
θJA
Thermal resistance
80
°C/W
ELECTRICAL CHARACTERISTICS
The elctrical characteristics listed below are actual tests (unless
otherwise stated) performed on each device with an automatic IC
tester prior to shipment. Performance of the device in automated
test set-up is not necessarily optimum. The NE568A is
layout-sensitive. Evaluation of performance for correlation to the
data sheet should be done with the circuit and layout of Figures 3, 4,
and 5 with the evaluation unit soldered in place. (Do not use a
socket!)
DC ELECTRICAL CHARACTERISTICS
VCC = 5V; TA = 25°C; fO = 70MHz, Test Circuit Figure 3, fIN = -20dBm, R4 = 3.9kΩ, unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
NE/SA568A
UNITS
MIN
TYP
MAX
VCC
Supply voltage
4.5
5
5.5
V
ICC
Supply current
54
70
mA
AC ELECTRICAL CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
SYMBOL
PARAMETER
TEST CONDITIONS
NE/SA568A
UNITS
MIN
TYP
MAX
fOSC
Maximum oscillator operating frequency3
150
MHz
Input signal level
50
–201
2000
+10
mVP-P
dBm
BW
Demodulated bandwidth
fO/7
MHz
Non-linearity5
Dev =
±20%, Input = -20dBm
1.0
4.0
%
Lock range2
Input = -20dBm
±25
±35
% of fO
Capture range2
Input = -20dBm
±20
±30
% of fO
TC of fO
Figure 3
100
ppm/
°C
RIN
Input resistance4
1
k
Output impedance
6
Demodulated VOUT
Dev =
±20% of fO measured at
Pin 14
0.40
0.52
VP-P
AM rejection
VIN = -20dBm (30% AM)
referred to
±20% deviation
50
dB
fO
Distribution6
Centered at 70MHz, R2 =
1.2k
Ω, C2 = 16pF, R4 = 3.9kΩ
(C2 + CSTRAY = 20pF)
-15
0
+15
%
fO
Drift with supply
4.5V to 5.5V
2
%/V
NOTE:
1. Signal level to assure all published parameters. Device will continue to function at lower levels with varying performance.
2. Limits are set symmetrical to fO. Actual characteristics may have asymmetry beyond the specified limits.
3. Not 100% tested, but guaranteed by design.
4. Input impedance depends on package and layout capacitances. See Figures 6 and 5.
5. Linearity is tested with incremental changes in inupt frequency and measurement of the DC output voltage at Pin 14 (VOUT). Non-linearity is
then calculated from a straight line over the deviation range specified.
6. Free-running frequency is measured as feedthrough to Pin 14 (VOUT) with no input signal applied.




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