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NE568A Datasheet(PDF) 4 Page - NXP Semiconductors

Part No. NE568A
Description  150MHz phase-locked loop
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Maker  PHILIPS [NXP Semiconductors]
Homepage  http://www.nxp.com
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 4 page
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Philips Semiconductors
Product specification
NE/SA568A
150MHz phase-locked loop
1996 Feb 1
4
C
9 +
1
2
p (50) (f
O)
F
At 70MHz, the calculated value is 45pF. Empirical results with the
test and application board were improved when a 47pF capacitor
was used.
The natural frequency for the loop filter is set by C10 and R1. If the
center frequency of the loop is 70MHz and the full demodulated
bandwidth is desired, i.e., fBW = fO/7 = 10MHz, and a value for R1 is
chosen, the value of C10 can be calculated.
C
10 +
1
2
p R
1 fBW
F
Also,
C
11 +
1
2
p350Wf
BW(Hz)
This capacitance determines the signal bandwidth of the output
buffer amplifier. (For further inofrmation see Philips application note
AN1881 “The NE568A Phase Locked Loop as a Wideband Video
Demodulator”.
Parts List and Layout 40MHz Application NE568AD
C1
100nF
±10%
Ceramic chip
1206
C21
18pF
±2%
Ceramic chip
0805
C22
16pF
±2%
Ceramic ORChip
C3
100nF
±10%
Ceramic chip
1206
C4
100nF
±10%
Ceramic chip
1206
C5
6.8
µF
±10%
Tantalum
35V
C6
100nF
±10%
Ceramic chip
1206
C7
100nF
±10%
Ceramic chip
1206
C8
100nF
±10%
Ceramic chip
1206
C9
47pF
±2%
Ceramic chip
0805 or 1206
C10
560pF
±2%
Ceramic chip
0805 or 1206
C11
47pF
±2%
Ceramic chip
0805 or 1206
C12
100nF
±10%
Ceramic chip
1206
C13
100nF
±10%
Ceramic chip
1206
R1
27
±10%
Chip CR32
1/4W
R2
1.2k
Trim pot
R33
43
±10%
Chip CR32
1/4W
R44
3.9k
±10%
Chip CR32
1/4W
R53
50
±10%
Chip CR32
1/4W
RFC15
10
µH
±10%
Surface mount
RFC25
10
µH
±10%
Surface mount
NOTES:
1. 18pF with Pin 12 ground and Pin 13 no connect (open).
2. C2 + CSTRAY = 16pF for temperature-compensated configuration
with R4 = 3.9kΩ.
3. For 50
Ω setup. R1 = 62Ω, R3 = 75Ω for 75Ω application.
4. For test configuration R4 = 0Ω (GND) and C2 = 18pF.
5. 0
Ω chip resistors (jumpers) may be substituted with minor degra-
dation of performance.
Parts List and Layout 70MHz Application NE568AN
C1
100nF
±10%
Ceramic chip
50V
C21
18pF
±2%
Ceramic chip
50V
C22
16pF
±2%
Ceramic chip
0805
C3
100nF
±10%
Ceramic chip
50V
C4
100nF
±10%
Ceramic chip
50V
C5
6.8
µF
±10%
Tantalum
35V
C6
100nF
±10%
Ceramic chip
50V
C7
100nF
±10%
Ceramic chip
50V
C8
100nF
±10%
Ceramic chip
50V
C9
47pF
±2%
Ceramic chip
50V
C10
560pF
±2%
Ceramic chip
50V
C11
47pF
±2%
Ceramic chip
50V
C12
100nF
±10%
Ceramic chip
50V
C13
100nF
±10%
Ceramic chip
50V
R1
27
±10%
Ceramic
chip
CR32
1/4W
R2
1.2k
Trim pot
R33
43
±10%
Ceramic
chip
CR32
1/4W
R44
3.9k
±10%
Ceramic
chip
CR32
1/4W
R53
50
±10%
Ceramic
chip
CR32
1/4W
RFC1
10
µH
±10%
Surface mount
RFC2
10
µH
±10%
Surface mount
NOTES:
1. 18pF with Pin 12 ground and Pin 13 no connect (open).
2. C2 + CSTRAY = 16pF for temperature-compensated configuration
with R4 = 3.9kΩ.
3. For 50
Ω setup. R1 = 62Ω, R3 = 75Ω for 75Ω application.
4. For test configuration R4 = 0Ω (GND) and C2 = 18pF.




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