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ISL6268 Datasheet(PDF) 7 Page - Intersil Corporation

Part # ISL6268
Description  High-Performance Notebook PWM Controller
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6268 Datasheet(HTML) 7 Page - Intersil Corporation

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7
FN6348.0
August 22, 2006
Theory of Operation
Modulator
The ISL6268 is a hybrid of fixed frequency PWM control, and
variable frequency hysteretic control. Intersil’s R3 technology
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The term “Ripple” in the name “Robust Ripple
Regulator” refers to the converter output inductor ripple
current, not the converter output ripple voltage. The R3
modulator synthesizes an AC signal VR, which is an ideal
representation of the output inductor ripple current. The
duty-cycle of VR is the result of charge and discharge
current through a ripple capacitor CR. The current through
CR is provided by a transconductance amplifier gm that
measures the VIN and VO pin voltages. The positive slope
of VR can be written as:
The negative slope of VR can be written as:
where gm is the gain of the transconductance amplifier.
A window voltage VW is referenced with respect to the error
amplifier output voltage VCOMP, creating an envelope into
which the ripple voltage VR is compared. The amplitude of
VW is set by a resistor connected across the FSET and GND
pins. The VR, VCOMP, and VW signals feed into a window
comparator in which VCOMP is the lower threshold voltage
and VW is the higher threshold voltage. Figure 2 shows
PWM pulses being generated as VR traverses the VW and
VCOMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of VR; the PWM switching frequency is inversely
proportional to the voltage between VW and VCOMP.
Power-On Reset
The ISL6268 is disabled until the voltage at the VCC pin has
increased above the rising power-on reset (POR) VCCR
threshold voltage. The controller will become once again
disabled when the voltage at the VCC pin decreases below
the falling POR VCCF threshold voltage.
EN, Soft-Start, and PGOOD
The ISL6268 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the inrush
current through the output capacitors as they charge to the
desired regulation voltage. When the EN pin is pulled above
the rising EN threshold voltage VENTHR the PGOOD
Soft-Start Delay TSS begins and the output voltage begins to
rise. The output voltage enters regulation in approximately
1.5ms and the PGOOD pin goes to high impedance once TSS
has elapsed.
The PGOOD pin indicates when the converter is capable of
supplying regulated voltage. The PGOOD pin is an
undefined impedance if VCC has not reached the rising POR
threshold VCCR, or if VCC is below the falling POR threshold
VCCF. The ISL6268 features a unique fault-identification
capability that can drastically reduce trouble-shooting time
and effort. The pull-down resistance of the PGOOD pin
corresponds to the fault status of the controller. During
soft-start or if an undervoltage fault occurs, the PGOOD
pull-down resistance is 95
Ω, or 32Ω for an overcurrent fault,
or 63
Ω for an overvoltage fault.
V
RPOS
g
m
() V
IN
V
OUT
()
=
(EQ. 1)
V
RNEG
g
m VOUT
=
(EQ. 2)
Ripple Capacitor Voltage CR
Error Amplifier Voltage VCOMP
Window Voltage VW
PWM
FIGURE 2. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
EN
VCC and PVCC
VOUT
PGOOD
1.5ms
2.75ms
FIGURE 3. SOFT-START SEQUENCE
ISL6268


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