Electronic Components Datasheet Search |
|
ISL6423BERZ Datasheet(PDF) 8 Page - Intersil Corporation |
|
ISL6423BERZ Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 16 page 8 FN6412.1 April 10, 2007 Typical Performance Curves FIGURE 2. OUTPUT CURRENT DERATING (EPTSSOP) FIGURE 3. OUTPUT CURRENT DERATING (4x4 QFN) 020 40 60 80 TEMPERATURE (°C) IOUT_max 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 020 40 60 80 TEMPERATURE (°C) IOUT_max 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0.80 Functional Pin Description SYMBOL FUNCTION SDA Bidirectional data from/to I2C bus. SCL Clock from I2C bus. VSW Input of the linear post-regulator. PGND Dedicated ground for the output gate driver of respective PWM. CS Current sense input; connect the sense resistor Rsc at this pin for desired peak overcurrent value for the boost FET. The set peak limit is effective in the static mode current limit only i.e., DCL = HIGH. SGND Small signal ground for the IC. TCAP Capacitor for setting rise and fall time of the output voltage. Typical value is 0.1µF. BYPASS Bypass capacitor for internal 5V. TXT TXT is the Tone Transmit signal input used to change the Tone Decoder Threshold from TXT = 0, 200mV max during Receive to TXT = 1, 400mV min during Transmit. VCC Main power supply to the chip. GATE This output drives the boost FET gate. The output is held low when VCC is below the UVLO threshold. VO Output voltage for the LNB is available at VO pin. ADDR0 & ADDR1 Logic combination at the ADDR0 & 1 can select four different chip select addresses. EXTM This pin can be used in two ways: 1) As an input for externally modulated Diseqc tone signal which is transferred to the symmetrically onto VOUT 2) Alternatively apply a Diseqc modulation envelope which modulates an internal tone and then transfers it symmetrically onto VOUT FLT This is an Open Drain output from the controller. When the FLT goes low it indicates that an Over Temperature, Over load fault, UVLO, or an I2C reset condition has occurred. The processor should then look at the I2C register to get the actual cause of the error. A high on the FLT indicates that the device is functioning normally. CPVOUT, CPSWIN CPSWOUT A 47n charge pump decoupling capacitor is to be connected to CPVOUT. Connect a 1.5n capacitor between CPSWIN and CPSWOUT SELVTOP When this pin is low the VOUT is in the 13V, 14V range selected by the I 2C bit VBOT. When this pin is high the 18V, 19V range selected by the I2C bit VTOP. The Voltage select pin enable VSPEN I2C bit must be set low for the SELVTOP pins to be active. Setting VSPEN high disables this pins and voltage selection will be done using the I2C bits VBOT and VTOP only. TDIN, TDOUT TDIN is the tone decoder input and TDOUT is the tone detector output. TDOUT is an open drain output |
Similar Part No. - ISL6423BERZ |
|
Similar Description - ISL6423BERZ |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |