7

FN7102.7

May 8, 2006

FIGURE 8. LOAD REGULATIONS

FIGURE 9. HTSSOP THERMAL RESISTANCE vs PCB AREA

(NO AIR FLOW)

FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE

Typical Performance Curves

526

508

506

504

024

6

520

512

516

135

524

518

510

514

522

0.1

-0.25

-0.3

-0.35

02

46

0

-0.15

135

-0.05

-0.2

-0.1

0.05

50

45

40

35

30

25

12

34567

89

CONDITION:

28-Pin HTSSOP THERMAL PAD

SOLDERED TO 2-LAYER PCB

WITH 0.039" THICKNESS AND

1 OZ. COPPER ON BOTH SIDES

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

3.5

2.5

2.0

1.0

0.5

0

0

25

50

75

100

150

AMBIENT TEMPERATURE (°C)

125

85

1.5

3.0

1.00

0.90

0.30

0

0

255075

100

150

AMBIENT TEMPERATURE (°C)

85

0.70

0.20

0.50

125

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.10

0.40

0.60

0.80

EL7566