10

FN7421.2

February 23, 2006

HIZ State

An internal pull-down resistor ensures the device will be

active with no connection to the HIZ pin. The HIZ state is

established within approximately 15ns (Figure 16) by placing

a logic high (>2V) on the HIZ pin. If the HIZ state is selected,

the output is a high impedance 1.4M

Ω with approximately

1.5pF in parallel with a 10

µA bias current from the output.

Use this state when more than one mux shares a common

output.

In the HIZ state the output is three-stated, and maintains its

high Z even in the presence of high slew rates. The supply

current during this state is same as the active state.

ENABLE and Power-down States

The enable pin is active low. An internal pull-down resistor

ensures the device will be active with no connection to the

ENABLE pin. The Power-down state is established within

approximately 80ns (Figure 14), if a logic high (>2V) is

placed on the ENABLE pin. In the Power-down state, the

output has no leakage but has a large variable capacitance

(on the order of 15pF), and is capable of being back-driven.

Under this condition, large incoming slew rates can cause

fault currents of tens of mA. Do not use this state as a high

impedance output when several MUX amps share the

same output line.

LE State

The EL4340 is equipped with a Latch Enable pin. A logic

high (>2V) on the LE pin latches the last logic state. This

logic state is preserved when cycling HIZ or ENABLE

functions.

Limiting the Output Current

No output short circuit current limit exists on these parts. All

applications need to limit the output current to less than

50mA. Adequate thermal heat sinking of the parts is also

required.

Application Example

Figure 22 illustrates the use of the EL4342, two ISL84517

SPST switches and one NC7ST00P5X NAND gate to mux 3

different component video signals and one RGB video

signal. The SPDT switches provide the sync signal for the

RGB video and disconnects the sync signal for the

component signal.

PC Board Layout

The AC performance of this circuit depends greatly on the

care taken in designing the PC board. The following are

recommendations to achieve optimum high frequency

performance from your PC board.

• The use of low inductance components such as chip

resistors and chip capacitors is strongly recommended.

• Minimize signal trace lengths. Trace inductance and

capacitance can easily limit circuit performance. Avoid

sharp corners, use rounded corners when possible. Vias

in the signal lines add inductance at high frequency and

should be avoided. PCB traces greater than 1" begin to

exhibit transmission line characteristics with signal rise/fall

times of 1ns or less. High frequency performance may be

degraded for traces greater than one inch, unless strip line

are used.

• Match channel-channel analog I/O trace lengths and

layout symmetry. This will minimize propagation delay

mismatches.

• Maximize use of AC de-coupled PCB layers. All signal I/O

lines should be routed over continuous ground planes (i.e.

no split planes or PCB gaps under these lines). Avoid vias

in the signal I/O lines.

• Use proper value and location of termination resistors.

Termination resistors should be as close to the device as

possible.

• When testing use good quality connectors and cables,

matching cable types and keeping cable lengths to a

minimum.

• Minimum of 2 power supply de-coupling capacitors are

recommended (1000pF, 0.01µF) as close to the devices

as possible - Avoid vias between the cap and the device

because vias add unwanted inductance. Larger caps can

be farther away. When vias are required in a layout, they

should be routed as far away from the device as possible.

• The NIC pins are placed on both sides of the input pins.

These pins are not internally connected to the die. It is

recommended these pins be tied to ground to minimize

crosstalk.

The QFN Package Requires Additional PCB Layout

Rules for the Thermal Pad

The thermal pad is electrically connected to V- supply

through the high resistance IC substrate. Its primary function

is to provide heat sinking for the IC. However, because of the

connection to the V- supply through the substrate, the

thermal pad must be tied to the V- supply to prevent

unwanted current flow to the thermal pad. Do not tie this pin

to GND as this could result in large back biased currents

flowing between GND and V-. The EL4342 uses the package

with pad dimensions of D2 = 2.48mm and E2 = 3.4mm.

Maximum AC performance is achieved if the thermal pad is

attached to a dedicated de-coupled layer in a multi-layered

PC board. In cases where a dedicated layer is not possible,

AC performance may be reduced at upper frequencies.

The thermal pad requirements are proportional to power

dissipation and ambient temperature. A dedicated layer

eliminates the need for individual thermal pad area. When a

dedicated layer is not possible a 1” x 1” pad area is sufficient

for the EL4342 that is dissipating 0.5W in +50°C ambient.

Pad area requirements should be evaluated on a case by

case basis.

EL4340, EL4342