7

FN7441.3

October 12, 2006

Serial Bus Operation

On the first negative clock edge after NSEnable goes low

read input from DATA. This DATA level should be 0 (write

into registers), READ is not supported. Read the next two

data bits on subsequent negative edges and interpret them

as the register to be filled. Reg 01 = R, 02 = G, 03 = B, 00

test use. Read the next five bits of data and send them to

register. At the end of each block of 8 bits, any further data is

treated as being a new word. Data entered is shifted directly

to the final registers as it is clocked in. Initial value of all

registers on power up is 0. It is the user's responsibility to

send complete patterns of 8 clock cycles even if the first bit

is set to 1. If less than 8 bits are sent, data will only be

partially shifted through the registers. The pattern of 8 starts

with NSEnable going low, so it is good practice to frame

each word within an NS enable burst.

TABLE 1. SERIAL BUS DATA

vwxyz

DELAY

00000

0

00001

2

00010

4

00011

6

00100

8

00101

10

00110

12

00111

14

01000

16

01001

18

01010

20

01011

22

01100

24

01101

26

01110

28

01111

30

10000

32

10001

34

10010

36

10011

38

10100

40

10101

42

10110

44

10111

46

11000

48

11001

50

11010

52

11011

54

11100

56

11101

58

11110

60

11111

62

NOTES:

Delay register word = 0abvwxyz

Red register - ab = 01

Green register - ab = 10

Blue register - ab = 11

vwxyz selects delay

TABLE 1. SERIAL BUS DATA (Continued)

vwxyz

DELAY

NSENABLE

SCLOCK

SDATA

A1

A0

D4

D3

D2

D1

D0

0

a

b

v

w

x

y

z

EL9115