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X5001P-2.7A Datasheet(PDF) 1 Page - Intersil Corporation |
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X5001P-2.7A Datasheet(HTML) 1 Page - Intersil Corporation |
1 / 20 page 1 ® FN8125.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. X5001 CPU Supervisor FEATURES • 200ms power-on reset delay •Low VCC detection and reset assertion —Five standard reset threshold voltages —Adjust low VCC reset threshold voltage using special programming sequence —Reset signal valid to VCC = 1V • Selectable nonvolatile watchdog timer —0.2, 0.6, 1.4 seconds —Off selection —Select settings through software • Long battery life with low power consumption —<50µA max standby current, watchdog on —<1µA max standby current, watchdog off • 2.7V to 5.5V operation • SPI mode 0 interface • Built-in inadvertent write protection —Power-up/power-down protection circuitry —Watchdog change latch • High reliability • Available packages —8 Ld TSSOP —8 Ld SOIC —8 Ld PDIP • Pb-free plus anneal available (RoHS compliant) DESCRIPTION This device combines three popular functions, Power- on Reset, Watchdog Timer, and Supply Voltage Supervision in one package. This combination lowers system cost, reduces board space requirements, and increases reliability. The watchdog timer provides an independent protec- tion mechanism for microcontrollers. During a system failure, the device will respond with a RESET signal after a selectable time out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user’s system is protected from low voltage condi- tions by the device’s low VCC detection circuitry. When VCC falls below the minimum VCC trip point, the system is reset. RESET is asserted until VCC returns to proper operating levels and stabilizes. Five industry standard VTRIP thresholds are available, however, Intersil’s unique circuits allow the threshold to be reprogrammed to meet custom requirements or to fine-tune the thresh- old for applications requiring higher precision. The device utilizes Intersil’s proprietary Direct Write™ cell for the watchdog timer control bits and the VTRIP storage element, providing a minimum endurance of 100,000 write cycles and a minimum data retention of 100 years. BLOCK DIAGRAM Watchdog Timer Data Register Command Decode & Control Logic SI SO SCK CS/WDI VCC Watchdog Transition Detector Reset & Watchdog Timebase Power-on/ Generation VTRIP + - RESET REset Low Voltage Data Sheet May 30, 2006 |
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