X40030V14-B datasheet(9/24 Pages) INTERSIL

Part #	X40030V14-B

Description	Triple Voltage Monitor with Integrated CPU Supervisor

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Manufacturer	INTERSIL [Intersil Corporation]

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9

FN8114.1

May 25, 2006

CONTROL REGISTER

The Control Register provides the user a mechanism

for changing the Block Lock and Watchdog Timer set-

tings. The Block Lock and Watchdog Timer bits are

nonvolatile and do not change when power is

removed.

The Control Register is accessed with a special pream-

ble in the slave byte (1011) and is located at address

1FFh. It can only be modified by performing a byte write

operation directly to the address of the register and only

one data byte is allowed for each register write opera-

tion. Prior to writing to the Control Register, the WEL

and RWEL bits must be set using a two step process,

with the whole sequence requiring 3 steps. See "Writing

to the Control Registers" on page 11.

The user must issue a stop, after sending this byte to

the register, to initiate the nonvolatile cycle that stores

WD1, WD0, PUP1, PUP0 and BP. The X40030,

X40031, X40034, X40035 will not acknowledge any

data bytes written after the first byte is entered.

The state of the Control Register can be read at any

time by performing a random read at address 1FFh,

using the special preamble. Only one byte is read by

each register read operation. The master should

supply a stop condition to be consistent with the bus

protocol.

RWEL: Register Write Enable Latch (Volatile)

The RWEL bit must be set to “1” prior to a write to the

Control Register.

Figure 5. Sample VTRIP Reset Circuit

7

6

543

21

0

PUP1 WD1 WD0

BP

0

RWEL WEL PUP0

1

6

2

7

14

13

9

8

X40030

VTRIP1

Adj.

VP

SDA

SCL

µC

Adjust

Run

V2FAIL

VTRIP2

Adj.

RESET

X40030, X40031, X40034, X40035

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