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P80CE558EBB Datasheet(PDF) 6 Page - NXP Semiconductors |
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P80CE558EBB Datasheet(HTML) 6 Page - NXP Semiconductors |
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6 / 72 page  Philips Semiconductors Preliminary specification P83CE558/P80CE558/P89CE558 Single-chip 8-bit microcontroller 1996 Aug 06 6 4.1 PIN DESCRIPTION SYMBOL PIN DESCRIPTION AVref– AVref+ 1 2 Low end of analog to digital conversion reference resistor High end of analog to digital conversion reference resistor. AVSS1 AVDD1 3 4 Analog ground for ADC Analog power supply (+5 V) for ADC AVSS2 AVDD2 77 76 Analog ground; for PLL oscillator Analog power supply; (+5 V) for PLL oscillator P5.7 – P5.0 5 – 12 Port 5 8-bit input port Port pin Alternative function P5.0–P5.7 Eight input channels to ADC (ADC0–ADC7) VDD1, VDD2, VDD3, VDD4 14, 28, 53, 66 Digital power supply: +5 V power supply pins during normal operation and power reduction modes. All pins must be connected. VSS1, VSS2 VSS3, VSS4 13, 29, 54, 67 Digital ground: circuit ground potential. All pins must be connected. ADEXS 15 Start ADC operation: Input starting analog to digital conversion triggered by a programmable edge (ADC operation can also be started by software). This pin must not float PWM0 16 Pulse width modulation output 0 PWM1 17 Pulse width modulation output 1 EW 18 Enable watchdog timer: Enable for T3 watchdog timer and disable Power-down Mode.This pin must not float. P4.0 – P4.7 19 – 22 24 – 27 Port 4 8-bit quasi-bidirectional I/O port Port pin Alternative function P4.0 CMSR0 } P4.1 CMSR1 } P4.2 CMSR2 } compare and set/reset P4.3 CMSR3 } outputs on a match with timer T2 P4.4 CMSR4 } P4.5 CMSR5 } P4.6 CMT0 } compare and toggle outputs P4.7 CMT1 } on a match with timer T2 RSTIN 30 Reset: Input to reset the P8xCE558. RSTOUT 23 Reset: Output of the P8xCE558 for resetting peripheral devices during initialization and Watchdog Timer overflow. P1.0 – P1.7 31 – 38 Port 1 8-bit quasi-bidirectional I/O port Port pin Alternative function P1.0 CT0I/INT2} P1.1 CT1I/INT3} : Capture timer inputs for P1.2 CT2I/INT4} timer T2 or external interrupt inputs P1.3 CT3I/INT5} P1.4 T2 : T2 event input, rising edge triggered P1.5 RT2 : T2 timer reset input, rising edge triggered P1.6 P1.7 SCL 39 I2C-bus serial clock I/O port SDA 40 I2C-bus serial data I/O port If SCL and SDA are not used, they must be connected to VSS. |
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