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X5083 Datasheet(PDF) 8 Page - Intersil Corporation |
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X5083 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 21 page 8 FN8127.3 June 15, 2006 SPI Serial Memory The memory portion of the device is a CMOS serial EEPROM array with Intersil’s block lock protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus. The device utilizes Intersil’s proprietary Direct Write™ cell, providing a minimum endurance of 100,000 cycles and a minimum data retention of 100 years. The device is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of many popular microcontroller families. The device monitors the bus and asserts RESET output if the watchdog timer is enabled and there is no bus activity within the user selectable time out period or the supply voltage falls below a preset minimum VTRIP. The device contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation. All instructions (Table 1), addresses and data are transferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is output on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off. Write Enable Latch The device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 7). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle. Status Register The RDSR instruction provides access to the status register. The status register may be read at any time, even during a write cycle. The status register is formatted as follows. Block Lock Memory Intersil’s block lock memory provides a flexible mechanism to store and lock system ID and parametric information. There are seven distinct block lock memory areas within the array which vary in size from one page to as much as half of the entire array. These areas and associated address ranges are block locked by writing the appropriate two byte block lock instruction to the device as described in Table 1 and Figure 9. Once a block lock instruction has been completed, that block lock setup is held in the nonvolatile status register until the next block lock instruction is issued. The sections of the memory array that are block locked can be read but not written until block lock is removed or changed. Status Register/Block Lock/WDT Byte 765 4 3 21 0 0 0 0 WD1 WD0 BL2 BL1 BL0 TABLE 1. INSTRUCTION SET AND BLOCK LOCK PROTECTION BYTE DEFINITION INSTRUCTION FORMAT INSTRUCTION NAME AND OPERATION 0000 0110 WREN: set the write enable latch (write enable operation) 0000 0100 WRDI: reset the write enable latch (write disable operation) 0000 0001 Write status instruction—followed by: Block lock/WDT byte: (See Figure 1) 000WD1 WD2000 --->no block lock: 00h-00h--->none of the array 000WD1 WD2001 --->block lock Q1: 0000h-00FFh--->lower quadrant (Q1) 000WD1 WD2010 --->block lock Q2: 0100h-01FFh--->Q2 000WD1 WD2011 --->block lock Q3: 0200h-02FFh--->Q3 000WD1 WD2100 --->block lock Q4: 0300h-03FFh--->upper quadrant (Q4) 000WD1 WD2101 --->block lock H1: 0000h-01FFh--->lower half of the array (H1) 000WD1 WD2110 --->block lock P0: 0000h-000Fh--->lower page (P0) 000WD1 WD2111 --->block lock Pn: 03F0h-03FFh--->upper page (PN) 0000 0101 READ STATUS: reads status register & provides write in progress status on SO pin 0000 0010 WRITE: write operation followed by address and data 0000 0011 READ: read operation followed by address X5083 |
Similar Part No. - X5083_06 |
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Similar Description - X5083_06 |
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