4

FN8128.3

June 1, 2006

Block Diagram

Watchdog

Timer Reset

Data

Register

Command

Decode &

Control

Logic

SI

SO

SCK

CS/WDI

Reset &

Watchdog

Timebase

Power-on and

Generation

+

-

RESET/RESET

Reset

Low Voltage

Status

Register

Protect Logic

4K Bits

4K Bits

8K Bits

Watchdog Transition

Detector

WP

X5163 = RESET

X5165 = RESET

Reset Logic

Pin Description

PIN

(SOIC/PDIP)

PIN TSSOP

NAME

FUNCTION

1

1

CS/WDI

Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance

state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.

CS LOW enables the device, placing it in the active power mode. Prior to the start of any

operation after power-up, a HIGH to LOW transition on CS is required Watchdog Input. A HIGH

to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a HIGH to LOW

transition within the watchdog time out period results in RESET/RESET going active.

22

SO

Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The

falling edge of the serial clock (SCK) clocks the data out.

36

WP

Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting

of the Watchdog Timer control and the memory write protect bits.

47

Ground

58

SI

Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this

pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),

addresses and data MSB first.

69

SCK

Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge

of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK

changes the data output on the SO pin.

7

13

RESET/

RESET

Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active

enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time out

period. A falling edge of CS will reset the Watchdog Timer. RESET/RESET goes active on power-

up at 1V and remains active for 200ms after the power supply stabilizes.

814

Supply Voltage

3-5,10-12

NC

No internal connections

X5163, X5165