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X9260 Datasheet(PDF) 5 Page - Intersil Corporation |
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X9260 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 23 page  5 FN8170.3 August 29, 2006 standby state. CS LOW enables the X9260, placing it in the active power mode. It should be noted that after a power-up, a HIGH to LOW transition on CS is required prior to the start of any operation. Potentiometer Pins RH, RL The RH and RL pins are equivalent to the terminal connections on a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RH and RL such that RH0 and RL0 are the terminals of POT 0 and so on. RW The wiper pin are equivalent to the wiper terminal of a mechanical potentiometer. Since there are 2 potentiometers, there are 2 sets of RW such that RW0 is the terminals of POT 0 and so on. Supply Pins SYSTEM SUPPLY VOLTAGE (VCC) AND SUPPLY GROUND (VSS) The VCC pin is the system supply voltage. The VSS pin is the system ground. Analog Supply Voltages (V+ and V -) These supplies are the analog voltage supplies for the potentiometer. The V+ supply is tied to the wiper switches while the V- supply is used to bias the switches and the internal P+ substrate of the integrated circuit. Both of these supplies set the voltage limits of the potentiometer. Other Pins NO CONNECT No connect pins should be left floating. This pins are used for Intersil manufacturing and testing purposes. HARDWARE WRITE PROTECT INPUT (WP) The WP pin when LOW prevents nonvolatile writes to the Data Registers. PRINCIPLES OF OPERATION Serial Interface The X9260 supports the SPI interface hardware conventions. The device is accessed via the SI input with data clocked in on the rising SCK. CS must be LOW and the HOLD and WP pins must be HIGH during the entire operation. The SO and SI pins can be connected together, since they have three state outputs. This can help to reduce system pin count. Array Description The X9260 is comprised of a resistor array (See Figure 1). The array contains the equivalent of 255 discrete resistive segments that are connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL inputs). At both ends of each array and between each resistor segment is a CMOS switch connected to the wiper (RW) output. Within each individual array only one switch may be turned on at a time. These switches are controlled by a Wiper Counter Register (WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to select, and enable, one of 256 switches (See Table 1). Power-up and Down Requirements. At all times, the voltages on the potentiometer pins must be less than V+ and more than V-. During power- up and power-down, VCC, V+, and V- must reach their final values within 1msecs of each other. The VCC ramp rate spec is always in effect. X9260 |
Similar Part No. - X9260_06 |
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Similar Description - X9260_06 |
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