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X9455WV24IZ-2.7 Datasheet(PDF) 6 Page - Intersil Corporation |
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X9455WV24IZ-2.7 Datasheet(HTML) 6 Page - Intersil Corporation |
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6 / 19 page  6 FN8202.1 July 28, 2006 SDA vs. SCL Timing WP, A0, A1, and A2 Pin Timing tSU:WPA (Note 5) A0, A1, A2 and WP Setup Time 600 ns tHD:WPA (Note 5) A0, A1, A2 and WP Hold Time 600 ns 2-Wire Interface Timing (s) (Continued) SYMBOL PARAMETER MIN MAX UNITS tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA (Input Timing) SDA (Output Timing) tF tLOW tBUF tAA tR tHD:WP SCL SDA IN WP, A0, A1, or A2 tSU:WP Clk 1 START STOP Increment/Decrement Timing SYMBOL PARAMETER MIN TYP (Note 4) MAX UNITS tCI CS to SCL Setup 600 ns tID (Note 5) SCL HIGH to U/D, DS0 or DS1 change 600 ns tDI (Note 5) U/D, DS0 or DS1 to SCL setup 600 ns tIL SCL LOW period 2.5 µs tIH SCL HIGH period 2.5 µs tIC SCL inactive to CS inactive (Nonvolatile Store Setup Time) 1 µs tCPHS CS deselect time (STORE) 10 ms tCPHNS (Note 5) CS deselect time (NO STORE) 1 µs tIW (Note 5) SCL to RW change 100 500 µs tCYC SCL cycle time 5 µs tR, tF (Note 5) SCL input rise and fall time 500 µs X9455 |
Similar Part No. - X9455WV24IZ-2.7 |
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Similar Description - X9455WV24IZ-2.7 |
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