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X9455YV24I-2.7 Datasheet(PDF) 11 Page - Intersil Corporation |
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X9455YV24I-2.7 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 19 page  11 FN8202.1 July 28, 2006 2-Wire serial interface Protocol Overview The device supports a bidirectional bus oriented protocol. The protocol defines any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. The device controlling the transfer is called the master and the device being controlled is called the slave. The master always initiates data transfers, and provides the clock for both transmit and receive operations. The X9455 operates as a slave in all applications. All 2-wire interface operations must begin with a START, followed by a Slave Address byte. The Slave Address selects the X9455, and specifies if a Read or Write operation is to be performed. All Communication over the 2-wire interface is conducted by sending the MSB of each byte of data first. Serial Clock and Data Data states on the SDA line can change only while SCL is LOW. SDA state changes while SCL is HIGH are reserved for indicating START and STOP conditions (See Figure 2). On power up of the X9455, the SDA pin is in the input mode. Serial Start Condition All commands are preceded by the START condition, which is a HIGH to LOW transition of SDA while SCL is HIGH. The device continuously monitors the SDA and SCL lines for the START condition and does not respond to any command until this condition has been met (See Figure 2). Serial Stop Condition All communications must be terminated by a STOP condition, which is a LOW to HIGH transition of SDA while SCL is HIGH. The STOP condition is also used to place the device into the Standby power mode after a read sequence. A STOP condition can only be issued after the transmitting device has released the bus (See Figure 2). Serial Acknowledge An ACK (Acknowledge), is a software convention used to indicate a successful data transfer. The transmitting device, either master or slave, releases the bus after transmitting eight bits. During the ninth clock cycle, the receiver pulls the SDA line LOW to acknowledge the reception of the eight bits of data (See Figure 3). The device responds with an ACK after recognition of a START condition followed by a valid Slave Address byte. A valid Slave Address byte must contain the Device Type Identifier 0101, and the Device Address bits matching the logic state of pins A2, A1, and A0 (See Figure 4). If a write operation is selected, the device responds with an ACK after the receipt of each subsequent eight-bit word. In the read mode, the device transmits eight bits of data, releases the SDA line, and then monitors the line for an ACK. The device continues transmitting data if an ACK is detected. The device terminates further data transmissions if an ACK is not detected. The master must then issue a STOP condition to place the device into a known state. SDA SCL START DATA DATA STOP STABLE CHANGE DATA STABLE FIGURE 2. VALID DATA CHANGES, START, AND STOP CONDITIONS SDA Output from Transmitter SDA Output from Receiver 8 1 9 START ACK SCL from Master FIGURE 3. ACKNOWLEDGE RESPONSE FROM RECEIVER X9455 |
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