X9520V20I-BT1 datasheet(10/30 Pages) INTERSIL

Part #	X9520V20I-BT1

Description	Triple DCP, POR, 2kbit EEPROM Memory, Dual Voltage Monitors

Download	30 Pages

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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10 / 30 page

10

FN8206.1

January 3, 2006

It should be noted that when reading out the data byte for

DCP0 (64 Tap), the upper two most significant bits are

“unknown” bits. For DCP1 (100 Tap), the upper most

significant bit is an “unknown”. For DCP2 (256 Tap) however,

all bits of the data byte are relevant (See Figure 10).

2KBIT EEPROM ARRAY

Operations on the 2kbit EEPROM Array, consist of either 1,

2 or 3 byte command sequences. All operations on the

EEPROM must begin with the Device Type Identifier of the

Slave Address set to 1010000. A Read or Write to the

EEPROM is selected by setting the LSB of the Slave

Address to the appropriate value R/W (Read = “1”,

Write = ”0”).

In some cases when performing a Read or Write to the

EEPROM, an Address Byte may also need to be specified.

This Address Byte can contain the values 00h to FFh.

EEPROM BYTE WRITE

In order to perform an EEPROM Byte Write operation to the

EEPROM array, the Write Enable Latch (WEL) bit of the

CONSTAT Register must first be set (See “BL1, BL0: Block

Lock protection bits - (Nonvolatile)” on page 13.)

For a write operation, the X9520 requires the Slave Address

Byte and an Address Byte. This gives the master access to

any one of the words in the array. After receipt of the

Address Byte, the X9520 responds with an

ACKNOWLEDGE, and awaits the next eight bits of data.

After receiving the 8 bits of the Data Byte, it again responds

with an ACKNOWLEDGE. The master then terminates the

transfer by generating a STOP condition, at which time the

X9520 begins the internal write cycle to the nonvolatile

memory (See Figure 11). During this internal write cycle, the

X9520 inputs are disabled, so it does not respond to any

requests from the master. The SDA output is at high

impedance. A write to a region of EEPROM memory which

has been protected with the Block-Lock feature (See “BL1,

BL0: Block Lock protection bits - (Nonvolatile)” on page 13.),

suppresses the ACKNOWLEDGE bit after the Address Byte.

EEPROM Page Write

In order to perform an EEPROM Page Write operation to the

EEPROM array, the Write Enable Latch (WEL) bit of the

CONSTAT Register must first be set (See “BL1, BL0: Block

Lock protection bits - (Nonvolatile)” on page 13.)

The X9520 is capable of a page write operation. It is initiated

in the same manner as the byte write operation; but instead

of terminating the write cycle after the first data byte is

transferred, the master can transmit an unlimited number of

8-bit bytes. After the receipt of each byte, the X9520

responds with an ACKNOWLEDGE, and the address is

internally incremented by one. The page address remains

constant. When the counter reaches the end of the page, it

“rolls over” and goes back to ‘0’ on the same page.

For example, if the master writes 12 bytes to the page

starting at location 11 (decimal), the first 5 bytes are written

to locations 11 through 15, while the last 7 bytes are written

to locations 0 through 6. Afterwards, the address counter

would point to location 7. If the master supplies more than 16

bytes of data, then new data overwrites the previous data,

one byte at a time (See Figure 13).

The master terminates the Data Byte loading by issuing a

STOP condition, which causes the X9520 to begin the

nonvolatile write cycle. As with the byte write operation, all

inputs are disabled until completion of the internal write

cycle. See Figure 12 for the address, ACKNOWLEDGE, and

data transfer sequence.

Stops and EEPROM Write Modes

Stop conditions that terminate write operations must be sent

by the master after sending at least 1 full data byte and

receiving the subsequent ACKNOWLEDGE signal. If the

master issues a STOP within a Data Byte, or before the

X9520 issues a corresponding ACKNOWLEDGE, the X9520

cancels the write operation. Therefore, the contents of the

EEPROM array does not change.

S

t

a

r

t

S

t

o

p

Slave

Address

Byte

Data

(n)

A

C

K

A

C

K

A

C

K

SDA Bus

Signals from the

Slave

Signals from the

Master

Data

(1)

A

C

K

(2 < n < 16)

FIGURE 12. EEPROM PAGE WRITE OPERATION

101000 00

X9520

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