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X9523V20IZ-B Datasheet(PDF) 9 Page - Intersil Corporation |
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X9523V20IZ-B Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 28 page  9 FN8209.1 January 3, 2006 It should be noted that all writes to any DCP of the X9523 are random in nature. Therefore, the Data Byte of consecutive write operations to any DCP can differ by an arbitrary number of bits. Also, setting the bits P1 = 1, P0 = 1 is a reserved sequence, and will result in no ACKNOWLEDGE after sending an Instruction Byte on SDA. The factory default setting of all “wiper position” settings is with 00h stored in the NVM of the DCPs. This corre- sponds to having the “wiper teminal” RWX (x = 1,2) at the “lowest” tap position, Therefore, the resistance between RWX and RLX is a minimum (essentially only the Wiper Resistance, RW). DCP Read Operation A read of DCPx (x = 1,2) can be performed using the three byte random read command sequence shown in Figure 10. The master issues the START condition and the Slave Address Byte 10101110 which specifies that a “dummy” write” is to be conducted. This “dummy” write operation sets which DCP is to be read (in the preceding Read operation). An ACKNOWLEDGE is returned by the X9523 after the Slave Address if received correctly. Next, an Instruction Byte is issued on SDA. Bits P1-P0 of the Instruction Byte determine which DCP “wiper position” is to be read. In this case, the state of the WT bit is “don’t care”. If the Instruction Byte format is valid, then another ACKNOWLEDGE is returned by the X9523. Following this ACKNOWLEDGE, the master immediately issues another START condition and a valid Slave address byte with the R/W bit set to 1. Then the X9523 issues an ACKNOWLEDGE followed by Data Byte, and finally, the master issues a STOP condition. The Data Byte read in this operation, corresponds to the “wiper position” (value of the WCR) of the DCP pointed to by bits P1 and P0. Slave Address Instruction Byte A C K A C K S t a r t S t o p Slave Address Data Byte A C K S t a r t SDA Bus Signals from the Slave Signals from the Master Figure 10. DCP Read Sequence “Dummy” write READ Operation 10 1 1 11 0 0 00 00 0 W T P 1 P 0 10 1 1 11 1 0 WRITE Operation - MSB LSB DCPx x = 1 x = 2 “-” = DON’T CARE S t a r t S t o p Slave Address Address Byte Data Byte A C K A C K A C K SDA Bus Signals from the Slave Signals from the Master Figure 11. EEPROM Byte Write Sequence Internal Device Address 1 01 0 0 0 0 0 WRITE Operation X9523 |
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