2

FN8218.3

March 8, 2006

Block Diagram

Ordering Information

PART NUMBER

PART MARKING

MAXIMUM PIXEL

RATE

TEMP RANGE

(°C)

PACKAGE

X98017L128-3.3

X98017L-3.3

170MHz

0 to 70

128 MQFP

X98017L128-3.3-Z (See Note)

X98017L-3.3Z

170MHz

0 to 70

128 MQFP (Pb-free)

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

G

RGB

G

RGB

V

V

PGA

8 bit ADC

+

V

CLAMP

R

R

V

V

PGA

8 bit ADC

+

V

CLAMP

B

B

V

V

PGA

8 bit ADC

+

V

CLAMP

Offset

DAC

Offset

DAC

Offset

DAC

ABLC™

ABLC™

ABLC™

8

10

8

10

8

10

8

B

8

B

8

G

8

G

8

R

8

R

SOG

SOG

HSYNC

HSYNC

VSYNC

VSYNC

CLOCKINV

XTAL

IN

XTAL

OUT

SCL

SDA

SADDR

Sync

Processing

Digital PLL

AFE Configuration

and Control

DATACLK

DATACLK

HS

OUT

VS

OUT

Serial

Interface

HSYNC

OUT

VSYNC

OUT

XTALCLK

OUT

X98017