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ISL88022IU8HEZ Datasheet(PDF) 4 Page - Intersil Corporation

Part # ISL88022IU8HEZ
Description  Triple Voltage Monitor with Adjustable Power-On-Reset and Undervoltage/ Overvoltage Monitoring Capability
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL88022IU8HEZ Datasheet(HTML) 4 Page - Intersil Corporation

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4
FN8226.1
September 18, 2006
Functional Description
The ISL88021 and ISL88022 devices incorporate such features
as Power-On-Reset control, Supply Voltage Supervision,
Undervoltage or Overvoltage Monitoring, and Manual Reset
Assertion.
The ISL88021 and ISL88022 devices provide common preset
threshold voltages on both VDD and V2MON and for an
optional resistor divider network on V3MON to provide custom
voltage monitoring of voltages greater than 0.6V. An optional
capacitor can be connected between the CPOR pin and GND to
increase the nominal 200ms tPOR delay. Figure 7 illustrates
operational functionality with a timing diagram.
Voltage Monitoring
During normal operation, the ISL88021 and ISL88022 monitor
the voltage levels on VDD, V2MON and V3MON. The
ISL88021 asserts reset if any one of these voltages fall below
their respective voltage trip points and in the case of ISL88022
above the voltage trip point on the V3MON input. The reset
signal effectively prevents the microprocessor from operating
during a power failure, brownout or over voltage condition. This
signal remains active until all monitored voltages meet all
voltage threshold requirements for the reset time delay period
tPOR. Note that both RESET and RESET signals are provided
for design flexibility. Figure 1 illustrates the VDD, V2MON and
V3MON input threshold voltages for the various available
options.
Power-On-Reset (POR)
Applying power to the ISL88021 and ISL88022 devices
activates a POR circuit which holds the RESET pin low once
VDD > 1V. This signal provides several benefits:
• It prevents the system microprocessor from starting to
operate with insufficient voltage.
• It prevents the processor from operating prior to
stabilization of the oscillator.
• It ensures that the monitored device is held out of operation
until internal registers are properly loaded.
• It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
When all of the monitored voltages meet their respective
input voltage requirements for the specified reset timeout
delay tPOR, the POR circuit simultaneously pulls the RST
output low and releases the RST output to allow the system
to begin operation.
Adjusting tPOR
On the ISL88021 and ISL88022, users can adjust the
Power-On-Reset timeout delay (tPOR) to many times the
nominal tPOR. Figure 2 illustrates the effect of capacitance
on the CPOR pin to ground, showing changing tPOR with a
graph normalized to 175ms for an open CPOR pin. The
maximum recommended capacitance that should be placed
on the CPOR pin is 50pF. NOTE: Care should be taken in
PCB layout and capacitor placement in order to eliminate
stray capacitance as much as possible, which contributes to
tPOR error.
MANUAL RESET
VMRL
MR Input Voltage Low
0.8
V
VMRH
MR Input Voltage High
VDD-0.6
V
tMR
MR Minimum Pulse Width
550
ns
RPU
Internal Pull-Up Resistor
20
k
Ω
Electrical Specifications
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
FIGURE 1. VDD, V2MON, V3MON VTH vs TEMP
0.000
0.500
1.000
1.500
2.000
2.500
3.000
3.500
4.000
4.500
5.000
-40
25
85
TEMPERATURE (°C)
Vth = 4.64V
Vth = 1.69V
Vth = 3.09V
Vth = 2.92V
Vth = 2.32V
Vth = 0.60V
FIGURE 2. NORMALIZED tPOR vs CPOR GRAPH
0
2
4
6
8
10
1
5
9 13 17 21 25 29 33 37 41 45
C
POR (pF)
ISL88021, ISL88022


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