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ISL6528CB Datasheet(PDF) 7 Page - Intersil Corporation

Part # ISL6528CB
Description  Dual Regulator - Standard Buck PWM and Linear Power Controller
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL6528CB Datasheet(HTML) 7 Page - Intersil Corporation

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7
FN9038.4
March 9, 2006
The linear regulator output voltage is also set by means of
an external resistor divider as shown in Figure 4. The two
resistors used to set the output voltage should not exceed a
parallel equivalent value, referred to as RFB, of 5kΩ. This
restriction is due to the manner of implementation of the soft-
start function. The following relationship must be met:
To ensure the parallel combination of the feedback resistors
meets this criteria, choose a target value for RFB of less than
5k
Ω and then apply the following equations:
where VOUT2 is the desired linear regulator output voltage
and VREF is the internal reference voltage, 0.8V. For an
output voltage of 0.8V, simply populate R5 with a value less
than 5k
Ω and do not populate R6.
Converter Shutdown
Pulling and holding the FB2 pin above a typical threshold of
1.28V will shutdown both regulators. Upon release of the
FB2 pin, the regulators enter into a soft-start cycle which
brings both outputs back into regulation.
PWM Controller Feedback Compensation
A simplified representation of the voltage-mode control loop
used for output regulation by the standard buck converter is
shown in Figure 5. The output voltage, VOUT, is fed back to
the negative input of the error amplifier which is regulated to
the reference voltage level, VREF. The error amplifier output,
VE/A, is compared with the triangle wave produced by the
oscillator, VOSC, to provide a pulse-width modulated (PWM)
signal from the PWM comparator. This signal is then used to
switch the MOSFET and produce a PWM waveform with an
amplitude of VIN at the PHASE node. The square-wave
PHASE voltage is then smoothed by the output filter, LOUT
and COUT, to produce a DC voltage level.
The modulator transfer function is defined as VOUT/VE/A.
The internal PWM comparator and driver circuits equate to a
DC gain block dominated by the supply voltage, VIN, divided
by the peak-to-peak magnitude of the triangle wave, VOSC.
The output filter components, LOUT and COUT, shape the
overall modulator small-signal transfer function by
contributing a double pole break frequency at FLC and a
zero at FESR.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks ZIN and ZFB. They provide the
link between the modulator transfer function and a
controllable closed loop transfer function of VOUT/VREF. The
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f0dB and 180
degrees.
DRIVE2
FB2
COUT2
Q2
ISL6528
VOUT2
+3.3VIN
R5
R6
FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE LINEAR
+
VOUT2
0.8
1 R5
R6
--------
+


×
=
RFB
R5 R6
×
R5 R6
+
---------------------- 5k
<
=
(EQ. 2)
R5
VOUT2
VREF
------------------- RFB
×
=
(EQ. 3)
R6
R5 VREF
×
VOUT2 VREF
----------------------------------------
=
(EQ. 4)
FLC
1
2
π
LO CO
×
×
----------------------------------------
=
FESR
1
2
π ESR C
O
×
×
-----------------------------------------
=
(EQ. 5)
(EQ. 6)
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
VOUT
VREF
LOUT
CO
ESR
VIN
VOSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
+
-
0.8V
R1
R3
R2
C3
C2
C1
COMP
VOUT
FB
ZFB
ISL6528
ZIN
COMP
DETAILED COMPENSATION COMPONENTS
PHASE
VE/A
+
-
+
+
ZFB
ZIN
OSC
ISL6528


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