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ISL6444 Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL6444 Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 19 page  11 FN9069.3 April 12, 2007 Gate Control Logic The gate control logic translates generated PWM signals into gate drive signals providing necessary amplification, level shift, and shoot-trough protection. Also, it bears some functions that help to optimize the IC performance over a wide range of the operational conditions. As MOSFET switching time can very dramatically from type to type and with the input voltage, the gate control logic provides adaptive dead time by monitoring real gate waveforms of both the upper and the lower MOSFETs. Dual-Step Conversion The ISL6444 dual channel controller can be used either in power systems with a single-stage power conversion when the battery power is converted into the desired output voltage in one step, or in the systems where some intermediate voltages are initially established. The choice of the approach may be dictated by the overall system design criteria or simply to be a matter of voltages available to the system designer, like in the case of PCI card applications. When the power input voltage is a regulated 5V or 3.3V system bus, the feed-forward ramp may become too shallow, which creates the possibility of duty-factor jitter especially in a noisy environment. The noise susceptibility when operating from low level regulated power sources can be improved by connecting the VIN pin to ground via a resistor. The internal pull-up current source of ~15 μA will create a voltage drop across the resistor. If this voltage is lower than 2.5V, the feed-forward ramp generator will be internally reconnected from the VIN pin to the VCC pin and the ramp slew rate will be doubled. Application circuits for dual-step power conversion are presented in Figure 10. Protections The converter output is monitored and protected against extreme overload, short circuit, overvoltage, and undervoltage conditions. A sustained overload on the output sets the PGOOD low and latches-off the whole chip. The controller operation can be restored by cycling the VCC voltage or an enable (EN) pin. Overcurrent Protection Both PWM controllers use the lower MOSFET’s on-resistance -- rDS(ON) to monitor the current for protection against shorted outputs. The sensed current from the ISEN pin is compared with a current set by a resistor connected from the OCSET pin to ground. Where, IOC is a desired overcurrent protection threshold and RCS is the value of the current sense resistor connected to the ISEN pin. If the lower MOSFET current exceeds the overcurrent threshold, a pulse skipping circuit is activated. The upper MOSFET will not be turned on as long as the sensed current is higher then the threshold value. This limits the current supplied by the DC voltage source. This condition keeps on for eight clock cycles after the overcurrent comparator was tripped for the first time. If after these first eight clock cycles, the current exceeds the overcurrent threshold again in a time interval of another eight clock cycles, the overcurrent protection latches and disables the chip. If the overcurrent condition goes away during the first eight clock cycles, normal operation is restored and the overcurrent circuit resets itself sixteen clock cycles after the overcurrent threshold was exceeded the first time, Figure 6. If load step is strong enough to pull output voltage lower than the undervoltage threshold, the chip shuts down immediately. Because of the nature of the used current sensing technique, and to accommodate wide range of the rDS(ON) variation, the value of the overcurrent threshold should represent overload current about 150%...180% of the nominal value. If accurate current protection is desired, a current sense resistor placed in series with the lower MOSFET source may be used. Overvoltage Protection Should the output voltage increase over 115% of the normal value due to the upper MOSFET failure, or other reasons, the overvoltage protection comparator will force the synchronous rectifier gate driver high. This action actively pulls down the output voltage and eventually attempts to blow the battery fuse. As soon as the output voltage drops below the threshold, the OVP comparator is disengaged. This OVP scheme provides a ‘soft’ crowbar function which helps to tackle severe load transients and does not invert the output voltage when activated -- a common problem for OVP schemes with a latch. R OCSET 11.2V R CS 100 Ω + () • I OC R • DS ON () ------------------------------------------------------------ = FIGURE 6. OVERCURRENT PROTECTION WAVEFORMS 3 1 2 SHUTDOWN IL VOUT Ch3 1.0A Ω Ch2 100mV M 10.0 μs Ch1 5.0V PGOOD 8 CLK ISL6444 |
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