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ISL6551IR Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6551IR Datasheet(HTML) 7 Page - Intersil Corporation |
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7 / 26 page  7 FN9066.5 January 3, 2006 Vsat_sinking (ISL6551IB) Vsat_low Sinking 20mA 0.035 V Sinking 200mA 0.31 V Vsat_sinking (ISL6551AB) Vsat_low Sinking 20mA 0.04 V Sinking 200mA 0.5 V SYNCHRONOUS SIGNALS (SYNC1, SYNC2) Maximum capacitive load (each) VDD = 12, F = 1MHz 20 pF PROGRAMMABLE DELAYS (RESDLY, LEB) (Note 4) Resonant Delay Adjust Range (Figure 7) 50 500 ns Resonant Delay tRESDLY R_RESDLY = 10K 55 ns R_RESDLY = 120K 488 ns Leading Edge Blanking Adjust Range (Figure 8) 50 300 ns Leading Edge Blanking tLEB R_LEB = 20K 64 ns R_LEB = 140K 302 ns R_LEB = 12V 0 ns LATCHING SHUTDOWN (LATSD) Fault Threshold VIN 3 V Fault_NOT Threshold VINN 1.9 V Time to Set latch (Note 4) TSET 415 ns ON/OFF (ONOFF) Turn-off Threshold OFF 0.8 V Turn-on Threshold ON 2 V CURRENT SHARE (SHARE, CS_COMP) (Note 4) Voltage Offset Between Error Amp Voltage of Master and Slave Vcs_offset SHARE = 30K 30 mV Maximum Source Current To External Reference Ics_source SHARE = 30K 190 µA Maximum Correctable Deviation In Reference Voltage Between Master and Slave SHARE = 30K, Rsource = 1K, OUTPUT REFERENCE = 1 to 5V, (See Figure 10) 190 mV Share/Adjust Loop Bandwidth CS BW CS_COMP = 0.1 µF 500 Hz DC OK (DCOK) Sink Current IDCOK 5mA Saturation Voltage VSATDCOK IDCOK = 5mA 0.4 V Input Reference Vref_in 1 5 V Threshold (relative to Vref_in) OV (Figure 11) 5 % Recovery (relative to Vref_in) OV (Figure 11) 3 % Threshold (relative to Vref_in) UV (Figure 11) -5 % Recovery (relative to Vref_in) UV (Figure 11) -3 % Transient Rejection (Note 4) TRej 100mV transient on Vout (system implicit rejection and feedback network dependence (Figure 12) 250 µs NOTE: 4. Guaranteed by design. Not 100% tested in production. Electrical Specifications These specifications apply for VDD = VDDP = 12V and TA = 0°C to 85°C (ISL6551IB) or -40°C to 105°C (ISL6551AB), Unless Otherwise Stated (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ISL6551 |
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