FMS3818

DATA SHEET

4

REV. 1.2.3 December 2004

Pin Descriptions

Pin

Name

Pin Number

Value

Pin Function Description

Clock and Data Inputs

CLK

26

CMOS

Clock Input. Pixel data is registered on the rising edge of CLK. CLK

should be driven by a dedicated buffer to avoid reflection induced jitter,

overshoot, and undershoot.

47-40

9-2

23-16

CMOS

Red, Green, and Blue Pixel Data Inputs. RGB digital inputs are

registered on the rising edge of CLK.

Controls

SYNC

11

CMOS

Sync Pulse Input. Bringing SYNC LOW, disables a current source which

registered on the rising edge of CLK. SYNC does not override any other

data and should be used only during the blanking interval. If sync pulses

are not required, SYNC should be connected to GND.

BLANK

10

CMOS

Blanking Input. When BLANK is LOW, pixel data inputs are ignored and

the D/A converter outputs are driven to the blanking level. BLANK is

registered on the rising edge of CLK.

Video Outputs

33

32

29

Red, Green, and Blue Current Outputs. Current source outputs can

drive VESA VSIS, and RS-343A/SMPTE-170M compatible levels into

doubly-terminated 75 Ohm lines. Sync pulses can be added to the green

Voltage Reference

35

+1.25 V

Voltage Reference Input/Output. Internal 1.25V voltage reference is

available on this pin. An external +1.25 Volt reference may be applied to

a 0.1µF ceramic capacitor is required.

36

348

Ω

Current-set Resistor Node. Full-scale output current of each D/A

converter is determined by the value of the resistor connected between

D/A full-scale current may also be calculated from:

(ohms) on each D/A converter.

COMP

34

0.1 µF

Compensation Capacitor Node. A 0.1 µF ceramic capacitor must be