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6

FMS6363 Rev. 1B

The same method can be used for biased signals with the addition

of a pull-up resistor to make sure the clamp never operates. The

internal pull-down resistance is 800kΩ ±20% so the external

resistance should be 7.5MΩ to set the DC level to 500mV. If a

pull-up resistance less than 7.5MΩ is desired, an external pull-

down can be added such that the DC input level is set to 500mV.

Figure 11. Biased SCART with

DC-coupled outputs

The same circuits can be used with AC-coupled outputs if desired.

Figure 12. DC-coupled inputs,

AC-coupled Outputs

Figure 13. AC-coupled inputs and outputs

Figure 14. Biased SCART with

AC-coupled outputs

NOTE: The video tilt or line time distortion will be dominated by the AC-coupling

capacitor. The value may need to be increased beyond 220uF in order to obtain satis-

factory operation in some applications.

Power Dissipation

The FMS6363 output drive configuration must be considered

when calculating overall power dissipation. Care must be taken

not to exceed the maximum die junction temperature. The fol-

lowing example can be used to calculate the FMS6363’s power

dissipation and internal temperature rise.

where

Board layout can also affect thermal characteristics. Refer to the

Layout Considerations Section for more information.

The FMS6363 is specified to operate with output currents typi-

cally less than 50mA, more than sufficient for a single (150Ω)

video load. Internal amplifiers are current limited to a maximum

of 100mA and should withstand brief duration short circuit con-

ditions, however this capability is not guaranteed.

Layout Considerations

General layout and supply bypassing play major roles in high

frequency performance and thermal characteristics. Fairchild

offers a demonstration board, FMS6363DEMO, to use as a

guide for layout and to aid in device testing and characterization.

The FMS6363DEMO is a 4-layer board with a full power and

ground plane. For optimum results, follow the steps below as a

basis for high frequency layout:

• Include 10µF and 0.1µF ceramic bypass capacitors

• Place the 10µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Connect all external ground pins as tightly as possible,

preferably with a large ground plane under the package

• Layout channel connections to reduce mutual trace inductance

• Minimize all trace lengths to reduce series inductances. If

routing across a board, place device such that longer traces

are at the inputs rather than the outputs.

If using multiple, low impedance DC coupled outputs, special

layout techniques may be employed to help dissipate heat.

If a multilayer board is used, a large ground plane directly

under the device will help reduce package case temperature.

For dual layer boards, an extended plane can be used.

Worse case additional die power due to DC loading can be

video load, add 25/(4*75) = 83mW, per channel.

75

Ω

LCVF

Bias

Input

75

Ω

0.1u

External Video

source must

be AC-coupled.

500mV +/-350mV

7.5M

Ω

DVD or

STB

SoC

DAC

Output

75

Ω

LCVF

Clamp

Inactive

0V - 1.4V

220u

DVD or

STB

SoC

DAC

Output

75Ω

LCVF

Clamp

Active

0.1u

0V - 1.4V

220u

75

Ω

LCVF

Clamp

Active

75

Ω

0.1u

External video

source must

be AC-coupled.

220u

500mV +/-350mV

7.5M

Ω