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BQ24721CRHBT Datasheet(PDF) 4 Page - Texas Instruments |
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BQ24721CRHBT Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 60 page  www.ti.com bq24721, bq24721C SLUS683C – NOVEMBER 2005 – REVISED DECEMBER 2006 DEVICE INFORMATION (continued) TERMINAL FUNCTIONS (continued) TERMINAL DESCRIPTION NO. NAME Battery to system switch driver output. Gate drive for the battery to system load BAT PMOS power FET to isolate the system from the battery to prevent current flow from the system to the battery, while allowing a low impedance path from battery to system while discharging the battery pack to the system load. Connect this pin directly to the gate of the input BAT PMOS power FET. Connect the source of 24 BATDRV the FET to the system load voltage node. Connect the drain of the FET to the battery pack positive node. Recommend placing a 10-k Ω resistor from the gate to the source of the BAT FET. An optional capacitor is placed from the gate to the source to slow-down the switching times. The internal gate drive is asymmetrical allowing a quick turn-off and slower turn-off in addition to the internal break-before-make logic with respect to the ACDRV. Alarm indicating charger status change, open-drain output. The ALARM is pulled low (LO) whenever the SMBus status register (0x13) has a change. The ALARM output is cleared (HI) when the SMBus 25 ALARM status (0x13) register is read, or there is a reset. This is used to alert the host and initiate an interrupt with the host instead of having to continuously poll the charger. A 10-k Ω pull-up resistor to the host controller supply rail is needed. Power ground. Ground connection for the high-current power converter nodes. Only connect to the 26 PGND AGND node by connecting to the PowerPAD™ underneath the IC. PWM low side driver output. Connect directly to the gate of the low-side NMOS power FET with a 27 LODRV short trace. Low-side driver gate voltage regulator and source for high-side driver bootstrap voltage. Add a 1- µF 28 REGN ceramic capacitor from REGN pin to PGND pin, close to the IC. Place a small signal Schottky diode from REGN to BTST for bootstrap voltage. High-side driver negative supply. Connect directly to the source of the high-side NMOS FET with a 29 PH short trace. This node is the common connection between the high-side FET, low-side FET, and output inductor. Connect a 0.1- µF boot-strap ceramic capacitor from BTST to PH. PWM high side driver output. Connect directly to the gate of the high-side NMOS power FET with a 30 HIDRV short trace. High-side driver positive supply, connect pos-side of boot-strap capacitor. Connect a 0.1- µF bootstrap capacitor from the BTST pin to the PH node. Also, connect a bootstrap diode with the anode connected to the REGN pin and the cathode connected to the BTST pin. An optional 4.7- Ω - 15-Ω 31 BTST series resistor is placed between the BTST pin and the bootstrap-diode/capacitor junction to slow-down the turn-on time of the high-side FET for reducing ringing due to high dv/dt of the phase node. IC power positive supply. Connect directly to the drain of the high-side NMOS power FET. Recommend placing at least a 10- µF ceramic capacitor directly from the drain of the high-side NMOS 32 PVCC power FET to PGND. Up to 40 µF may be needed to prevent resonance filtering inductance. Also, a 0.1- µF decoupling ceramic capacitor is recommended. 4 Submit Documentation Feedback |
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