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ISL9000IRKKZ Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL9000IRKKZ Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 11 page 8 FN9217.3 August 2, 2006 Pin Description Typical Application PIN # PIN NAME TYPE DESCRIPTION 1 VIN Analog I/O Supply Voltage/LDO Input: Connect a 1 μF capacitor to GND. 2 EN1 Low Voltage Compatible CMOS Input LDO-1 Enable. 3 EN2 Low Voltage Compatible CMOS Input LDO-2 Enable. 4 CBYP Analog I/O Reference Bypass Capacitor Pin: Optionally connect capacitor of value 0.01 μF to 1μF between this pin and GND to tune in the desired noise and PSRR performance. 5 CPOR Analog I/O POR2 Delay Setting Capacitor Pin: Connect a capacitor between this pin and GND to delay the POR2 output release after LDO-2 output reaches 94% of its specified voltage level. (200ms delay per 0.01 μF). 6 GND Ground GND is the connection to system ground. Connect to PCB Ground plane. 7POR1 Open Drain Output (1mA) Open-drain POR Output for LDO-1 (active-low): Internally connected to VO1 through 100k Ω resistor. 8POR2 Open Drain Output (1mA) Open-drain POR Output for LDO-2 (active-low): Internally connected to VO2 through 100k Ω resistor. 9VO2 Analog I/O LDO-2 Output: Connect capacitor of value 1 μF to 10μF to GND (1μF recommended). 10 VO1 Analog I/O LDO-1 Output: Connect capacitor of value 1 μF to 10μF to GND (1μF recommended). C1, C4, C5: 1µF X5R ceramic capacitor C2: 0.1µF X7R ceramic capacitor ISL9000 VIN EN1 EN2 CBYP CPOR VO1 VO2 POR2 POR1 GND 10 9 8 7 6 1 2 3 4 5 VIN (2.3-6.5V) Enable 1 Enable 2 Vout 1 Vout 2 Reset 1 Reset 2 C1 C2 C3 C4 C5 C3: 0.01µF X7R ceramic capacitor OFF ON OFF ON (200ms delay, C3 = 0.01µF) (2ms delay) Vout 2 too low Vout 2 OK Vout 1 too low Vout 1 OK ISL9000 |
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