8

FN9221.1

March 6, 2006

Application Information

MOSFET and Driver Selection

The parasitic inductances of the PCB and of the power

devices’ packaging (both upper and lower MOSFETs) can

cause serious ringing, exceeding absolute maximum rating

of the devices. The negative ringing at the edges of the

PHASE node could increase the bootstrap capacitor voltage

through the internal bootstrap diode, and in some cases, it

may overstress the upper MOSFET driver. Careful layout,

proper selection of MOSFETs and packaging, as well as the

proper driver can go a long way toward minimizing such

unwanted stress.

a much better match (for the reasons discussed) for the

ISL6609A. Low-profile MOSFETs, such as Direct FETs and

multi-SOURCE leads devices (SO-8, LFPAK, PowerPAK),

have low parasitic lead inductances and can be driven by

either ISL6609 or ISL6609A (assuming proper layout

design). The ISL6609, missing the 3

Ω integrated BOOT

resistor, typically yields slightly higher efficiency than the

ISL6609A.

Layout Considerations

A good layout helps reduce the ringing on the switching

node (PHASE) and significantly lower the stress applied to

the output drives. The following advice is meant to lead to an

optimized layout:

• Keep decoupling loops (VCC-GND and BOOT-PHASE) as

short as possible.

• Minimize trace inductance, especially on low-impedance

lines. All power traces (UGATE, PHASE, LGATE, GND,

VCC) should be short and wide, as much as possible.

• Minimize the inductance of the PHASE node. Ideally, the

source of the upper and the drain of the lower MOSFET

should be as close as thermally allowable.

• Minimize the current loop of the output and input power

trains. Short the source connection of the lower MOSFET

to ground as close to the transistor pin as feasible. Input

capacitors (especially ceramic decoupling) should be

placed as close to the drain of upper and source of lower

MOSFETs as possible.

In addition, connecting the thermal pad of the QFN package

to the power ground through a via, or placing a low noise

copper plane underneath the SOIC part is recommended for

high switching frequency, high current applications. This is to

improve heat dissipation and allow the part to achieve its

full thermal potential.

Upper MOSFET Self Turn-On Effects at Startup

Should the driver have insufficient bias voltage applied, its

outputs are floating. If the input bus is energized at a high

dV/dt rate while the driver outputs are floating, because of

UGATE could momentarily rise up to a level greater than the

threshold voltage of the MOSFET. This could potentially turn

on the upper switch and result in damaging inrush energy.

Therefore, if such a situation (when input bus powered up

before the bias of the controller and driver is ready) could

conceivably be encountered, it is a common practice to

upper MOSFET to suppress the Miller coupling effect. The

value of the resistor depends mainly on the input voltage’s

threshold of the upper MOSFET. A higher dV/dt, a lower

FET will require a smaller resistor to diminish the effect of

the internal capacitive coupling. For most applications, a

5k to 10k

Ω resistor is typically sufficient, not affecting normal

performance and efficiency.

The coupling effect can be roughly estimated with the

following equations, which assume a fixed linear input ramp

and neglect the clamping effect of the body diode of the

upper drive and the bootstrap capacitor. Other parasitic

components such as lead inductances and PCB

capacitances are also not taken into account. These

equations are provided for guidance purpose only.

FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH

FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH

Q1

D

S

G

BOOT

PHASE

VCC

UGATE

VCC

Q2

D

S

G

GND

LGATE

ISL6609, ISL6609A