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ISL9000IRGPZ Datasheet(PDF) 10 Page - Intersil Corporation |
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ISL9000IRGPZ Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 11 page 10 FN9217.3 August 2, 2006 If EN1 is brought high, and EN2 goes high before the VO1 output stabilizes, the ISL9000 delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high before VO2 starts its output ramp, then VO1 turns on first and, the ISL9000 delays the VO2 turn-on until the VO1 output reaches its target level. If EN2 is brought high, and EN1 goes high after VO2 starts its output ramp, then the ISL9000 immediately starts to ramp up the VO1 output. If both EN1 and EN2 are brought high at the same time, the VO1 output has priority, and is always powered up first. During operation, whenever the VIN voltage drops below about 1.8V, the ISL9000 immediately disables both LDO outputs. When VIN rises back above 2.1V, the device re-initiates its start-up sequence and LDO operation will resume automatically. Reference Generation The reference generation circuitry includes a trimmed bandgap, a trimmed voltage reference divider, a trimmed current reference generator, and an RC noise filter. The filter includes the external capacitor connected to the CBYP pin. A 0.01 μF capacitor connected CBYP implements a 100Hz lowpass filter, and is recommended for most high performance applications. For the lowest noise application, a 0.1 μF or greater CBYP capacitor should be used. This filters the reference noise below the 10Hz to 1kHz frequency band, which is crucial in many noise-sensitive applications. The bandgap generates a zero temperature coefficient (TC) voltage for the reference divider. The reference divider provides the regulation reference, POR detection thresholds, and other voltage references required for current generation and over-temperature detection. The current generator provides the references required for adaptive biasing as well as references for LDO output current limit and thermal shutdown determination. LDO Regulation and Programmable Output Divider The LDO Regulator is implemented with a high-gain operational amplifier driving a PMOS pass transistor. The design of the ISL9000 provides a regulator that has low quiescent current, fast transient response, and overall stability across all operating and load current conditions. LDO stability is guaranteed for a 1 μF to 10μF output capacitor that has a tolerance better than 20% and ESR less than 200m Ω. The design is performance-optimized for a 1μF capacitor. Unless limited by the application, use of an output capacitor value above 4.7 μF is not normally needed as LDO performance improvement is minimal. Each LDO uses an independently trimmed 1V reference. An internal resistor divider drops the LDO output voltage down to 1V. This is compared to the 1V reference for regulation. The resistor division ratio is programmed in the factory to one of the following output voltages: 1.5V, 1.8V, 1.85, 2.5V, 2.6V, 2.7V, 2.8V, 2.85V, 2.9, 3.0, and 3.3V. Power-On Reset Generation Each LDO has a separate Power-on Reset signal generation circuit which outputs to the respective POR pins. The POR signal is generated as follows: A POR comparator continuously monitors the output of each LDO. The LDO enters a power-good state when the output voltage is above 94% of the expected output voltage for a period exceeding the LDO PGOOD entry delay time (see below). In the power-good state, the open-drain PORx output is in a high-impedance state. An internal 100k Ω pull-up resistor pulls the pin up to the respective LDO output voltage. An external resistor can be added between the PORx output and the LDO output for a faster rise time, however, the PORx output should not connect through an external resistor to a supply greater than the associated LDO voltage. The power-good state is exited when the LDO output falls below 90% of the expected output voltage for a period longer than the PGOOD exit delay time. While power-good is false, the ISL9000 pulls the respective POR pin low. For LDO-1, the PGOOD entry delay time is fixed at about 2ms while the PGOOD exit delay is about 25 μs. For LDO-2, the PGOOD entry and exit delays are determined by the value of the external capacitor connected to the CPOR pin. For a 0.01 μF capacitor, the entry and exit delays are 200ms and 25 μs respectively. Larger or smaller capacitor values will yield proportionately longer or shorter delay times. The POR exit delay should never be allowed to be less than 10 μs to ensure sufficient immunity against transient induced false POR triggering. Overheat Detection The bandgap provides a proportional-to-temperature current that is indicative of the temperature of the silicon. This current is compared with references to determine if the device is in danger of damage due to overheating. When the die temperature reaches about 145°C, one or both of the LDO’s momentarily shut down until the die cools sufficiently. In the overheat condition, only the LDO sourcing more than 50mA will be shut off. This does not affect the operation of the other LDO. If both LDOs source more than 50mA and an overheat condition occurs, both LDO outputs are disabled. Once the die temperature falls back below about 110°C, the disabled LDO(s) are re-enabled and soft-start automatically takes place. The ISL9000 provides short-circuit protection by limiting the output current to about 475mA. If short circuited, an output current of 475mA will cause die heating. If the short circuit lasts long enough, the overheat detection circuit will turn off the output. ISL9000 |
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