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TLV320AIC3106IRGZT Datasheet(PDF) 10 Page - Texas Instruments |
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TLV320AIC3106IRGZT Datasheet(HTML) 10 Page - Texas Instruments |
10 / 99 page www.ti.com AUDIO DATA SERIAL INTERFACE TIMING DIAGRAM WCLK SDOUT BCLK SDIN td(WS) td(DO-WS) td(DO-BCLK) ts(DI) th(DI) TIMING CHARACTERISTICS (1) WCLK SDOUT BCLK SDIN td(WS) td(WS) td(DO-BCLK) ts(DI) th(DI) TLV320AIC3106 SLAS509A – DECEMBER 2006 – REVISED APRIL 2007 Figure 1. I2S/LJF/RJF Timing in Master Mode All specifications typical at 25 °C, DVDD = 1.8 V IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX td (WS) ADWS/WCLK delay time 50 15 ns td (DO-WS) ADWS/WCLK to DOUT delay time 50 20 ns td (DO-BCLK) BCLK to DOUT delay time 50 15 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 30 10 ns tf Fall time 30 10 ns (1) All timing specifications are measured at characterization but not tested at final test. Figure 2. DSP Timing in Master Mode 10 Submit Documentation Feedback |
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