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DEVICE INFORMATION

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EN

FB

COMP

VDD

UVLO

RT

ILIM

GND

HDRV

SW

BOOT

LDRV

BP

SS_SEL

PGOOD

SYNC

PW PACKAGE

(TOP VIEW)

TPS40195

SLUS720 – FEBRUARY 2007

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Gate drive voltage for the high-side N-channel MOSFET. A 100-nF capacitor (typical) must be connected

BOOT

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I

between this pin and SW.

Output bypass for the internal regulator. Connect a capacitor of 1-

µF (or greater) from this pin to GND.

BP

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O

Larger capacitors, up to 4.7

µF will improve noise performance with a low side FET Qg over 25nC. Do not

connect to VDD or drive externally.

COMP

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O

Output of the error amplifier.

Logic level input which starts or stops the controller from an external user command. A high-level turns the

EN

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controller on. A weak internal pull-up holds this pin high so that the pin may be left floating if this function is

not used. Observe interface cautions in applications information.

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal

FB

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I

reference voltage (591 mV typical)

GND

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-

Common reference for the device

HDRV

16

O

Gate drive output to the high-side N-channel FET.

Current limit. Sets short circuit protection threshold for low-side MOSFET sensing. Connect a resistor to

ILIM

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GND to set the threshold

LDRV

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O

Gate drive output for the low side N-channel FET.

Open drain power good output. Pulls low under any fault condition, soft start is active or if the FB pin

PGOOD

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O

voltage is outside the specified voltage window.

Switching frequency programming pin. Also determines function of SYNC pin. Connected to GND for 250

kHz operation and using SYNC as an output. Connect to BP for 500-kHz operation and using SYNC as an

RT

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output. Connect a resistor to GND to program a frequency and allow SYNC to accept synchronization

pulses. If RT is used to program a switching frequency and SYNC is not to be used to synchronize the

converter to an external clock, connect SYNC to GND.

Soft-start timing selection. Can be connected to GND, BP or left floating to select a soft start time that is

SS_SEL

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proportional to the switching frequency.

Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying

SW

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high-side MOSFET driver

Bidirectional synchronization I/O pin. SYNC is an output when the RT pin is connected to BP or GND. The

output is a falling edge signal 180

° out-of-phase with the rising edge of HDRV. In this mode SYNC can be

used to drive the SYNC pin of an additional TPS40195 device whose RT pin is tied to GND through a

resistor, providing two converters that operate 180

° out-of-phase to one another. SYNC may be used as an

SYNC

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I/O

input to synchronize to an external system clock if RT is connected to GND through a resistor as well. The

device synchronizes to the falling edge of the external clock signal. If RT is used to program a switching

frequency and SYNC is not to be used to synchronize the converter to an external clock, connect SYNC to

GND.

Programmable UVLO pin for the controller. A resistor divider on this pin to VDD sets the converter turn on

UVLO

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voltage and the hysteresis for turn-off.

VDD

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Power input to the controller. A 100 nF bypass capacitor should be connected closely from this pin to GND.

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