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TRF3761-DIRHARG4 Datasheet(PDF) 9 Page - Texas Instruments |
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TRF3761-DIRHARG4 Datasheet(HTML) 9 Page - Texas Instruments |
9 / 56 page www.ti.com TRF3761-C ELECTRICAL CHARACTERISTICS TRF3761 SLWS181F – OCTOBER 2005 – REVISED JANUARY 2007 Supply voltage = V CC = 5V, TA = –40 to 85 °C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT NOISE CHARACTERISTICS 100kHz offset –119.5 600kHz offset –138.8 VCO phase noise, fVCO = 1723MHz, 1MHz offset -143.9 dBc/Hz Free running VCO direct output fO = 1700MHz 6MHz offset –155.3 10MHz offset –157.5 100kHz offset –126 600kHz offset –145.2 VCO phase noise, fVCO = 1723MHz, 1MHz offset –149.5 dBc/Hz Free running VCO divide-by-2 output fO = 861.5 MHz 6MHz offset –157.2 10MHz offset –158 100kHz offset –133 600kHz offset -151 VCO phase noise, fVCO = 1723MHz, 1MHz offset -153.8 dBc/Hz Free running VCO divide-by-4 output fO = 430.75 MHz 6MHz offset –156 10MHz offset –156.5 1kHz offset –85 600kHz offset –138.3 4 VCO phase noise, fVCO = 1723MHz, dBc/Hz Closed loop phase noise direct output(1)(2)(3) fO = 1723MHz, 1MHz offset –142.6 8 10MHz offset –157.3 RMS phase error 100Hz to 10MHz 0.87 ° Closed loop phase noise direct output(3) 1kHz offset –90.1 600kHz offset –145 VCO phase noise, fVCO = 1723MHz, dBc/Hz Closed loop phase noise divide-by-2 output(1)(2)(3) fO = 861.5 MHz 1MHz offset –148.6 10MHz offset –158 RMS phase error 100Hz to 10MHz 0.53 ° Closed loop phase noise divide-by-2 output(3) 1kHz offset –96.2 600kHz offset –151 VCO phase noise, fVCO = 1723MHz, dBc/Hz Closed loop phase noise divide-by-4 output(1)(2)(3) fO = 430.75 MHz 1MHz offset –153 10MHz offset –156 RMS phase error 100Hz to 10MHz 0.33 ° Closed loop phase noise divide-by-4 output(3) VCO gain, Kv VCO free running 23 MHz/V Reference spur(2) –80 dBc (1) See Application Circuit Figure 78. (2) PFD = 200kHz, Loop Filter BW = 15kHz, Output frequency step = 200kHz. (3) Reference oscillator RMS phase error = 0.008250 °, RMS jitter = 881.764 fs. 9 Submit Documentation Feedback |
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