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PCA1070P Datasheet(PDF) 6 Page - NXP Semiconductors |
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PCA1070P Datasheet(HTML) 6 Page - NXP Semiconductors |
6 / 36 page 1997 Jun 20 6 Philips Semiconductors Product specification Multistandard programmable analog CMOS transmission IC PCA1070 DC STARTING AND SETTLING TIME The IC is equipped with circuitry for fast DC start-up. This circuit is automatically activated as soon as VDD reaches 3 V after hook-off, and is deactivated when VSLPE drops below 5.9 V. This ensures that only a relatively short time is needed to reach the default DC setting (VSLPE) of the circuit and that VDD will not exceed the maximum permitted voltage of 6 V. The start-up circuit can also be activated under software control by setting bit code DST to logic 1 via the I2C-bus. The start-up time can be optimized by programming the bit code DST to logic 1 during the start-up procedure. In practice this is possible as soon as the microcontroller has become operational. The DST bit can also be used to quickly restore the DC settings (VSLPE) after long line breaks or during reprogramming of VSLPE. It should be noted that the AC impedance into pin LN is reduced considerably when DST = 1. Power control INTERNAL RESET PCA1070 The PCA1070 has an internal reset circuit that monitors the supply voltage VDD. If VDD is below the threshold level (1.2 V) then the circuit is in reset-mode. In this mode the current consumption is low and the internal reset is active and writes the default values into all registers. The status bit PRES will be set to logic 1. The microcontroller can read this bit via the I2C-bus interface; once read it will be set to logic 0 again. When VDD passes the threshold (increasing VDD), the circuit becomes partly active and the internal ring/speech detector will be activated (see Section “Start-up and switch-off behaviour”). RESET OUTPUT FOR MICROCONTROLLER The voltage at pin VMC (microcontroller supply voltage) is monitored by a reset circuit. If VVMC is below the threshold level the output RMC is set to logic 1. This threshold level is 2 V in the normal operating and power-down mode and 2.1 V in the standby mode (see Fig.4). POWER-DOWN/STANDBY MODES The circuit can be set in power-down or standby mode. These modes are intended for use with pulse dialling during long line breaks and applications with memory retention. With control bits PDx = 01, the circuit is in the power-down mode; the typical current consumption at pin VDD is reduced from IDD = 2.3 mA to 30 µA; the typical current consumption at pin VMC is 4 µA. When PDx = 11 the circuit is in the standby mode and IDD and IVMC are reduced to 2 µA. In both conditions (power-down and standby) the voltage stabilizer will be disabled. START-UP AND SWITCH-OFF BEHAVIOUR This description refers to the basic application where VDD and VMC are connected together and one supply capacitor is used (see Fig.8). Fig.4 VMC timing diagram. handbook, halfpage MGE339 0 VVMC RMC logic 1 low voltage condition VRESET logic 0 |
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