AD1974 datasheet(5/24 Pages) AD

Part #	AD1974

Description	4 ADC with PLL, 192 kHz, 24-Bit Codec

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AD1974

Rev. 0 | Page 5 of 24

POWER SUPPLY SPECIFICATIONS

Table 5.

Parameter

Conditions/Comments

Min

Typ

Max

Unit

SUPPLIES

Voltage

DVDD

3.0

3.3

3.6

V

AVDD

3.0

3.3

3.6

V

Digital Current

MCLK = 256 fS

Normal Operation

fS = 48 kHz

56

mA

fS = 96 kHz

65

mA

fS = 192 kHz

95

mA

Power-Down

fS = 48 kHz to 192 kHz

2.0

mA

Analog Current

Normal Operation

74

mA

Power-Down

23

mA

DISSIPATION

Operation

MCLK = 256 fS, 48 kHz

All Supplies

429

mW

Digital Supply

185

mW

Analog Supply

244

mW

Power-Down, All Supplies

83

mW

POWER SUPPLY REJECTION RATIO

Signal at Analog Supply Pins

1 kHz, 200 mV p-p

50

dB

20 kHz, 200 mV p-p

50

dB

DIGITAL FILTERS

Table 6.

Parameter

Mode

Factor

Min

Typ

Max

Unit

ADC DECIMATION FILTER

All modes @ 48 kHz

Pass Band

0.4375 fS

21

kHz

Pass-Band Ripple

±0.015

dB

Transition Band

0.5 fS

24

kHz

Stop Band

0.5625 fS

27

kHz

Stop-Band Attenuation

79

dB

Group Delay

22.9844 fS

479

μs

TIMING SPECIFICATIONS

−40°C < TA < +130°C, DVDD = 3.3 V ± 10%.

Table 7.

Parameter

Condition

Comments

Min

Max

Unit

INPUT MASTER CLOCK (MCLK)

AND RESET

tMH

MCLK duty cycle

ADC clock source = PLL clock @ 256 fS, 384 fS, 512 fS, 768 fS

40

60

%

tMH

ADC clock source = direct MCLK @ 512 fS (bypass

on-chip PLL)

40

60

%

fMCLK

MCLK frequency

PLL mode, 256 fS reference

6.9

13.8

MHz

fMCLK

Direct 512 fS mode

27.6

MHz

tPDR

Low

15

ns

tPDRR

Recovery

Reset to active output

4096

tMCLK

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