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MM74HCT574N Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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MM74HCT574N Datasheet(HTML) 4 Page - Fairchild Semiconductor |
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4 / 9 page  www.fairchildsemi.com 4 AC Electrical Characteristics MM74HCT573 VCC 5.0V, tr tf 6 ns, TA 25qC (unless otherwise specified) AC Electrical Characteristics MM74HCT573 VCC 5.0V r 10%, tr tf 6 ns (unless otherwise specified) Note 5: CPD determines the no load dynamic power consumption, PD CPD VCC2 fICC VCC, and the no load dynamic current consumption, IS CPD VCC fICC. Symbol Parameter Conditions Typ Guaranteed Limit Units tPHL Maximum Propagation Delay CL 45 pF 17 27 ns tPLH Data to Output tPHL Maximum Propagation Delay CL 45 pF 16 27 ns tPLH Latch Enable to Output tPZH Maximum Enable Propagation Delay CL 45 pF 21 30 ns tPZL Control to Output RL 1 k: tPHZ Maximum Disable Propagation Delay CL 5 pF 14 23 ns tPLZ Control to Output RL 1 k: tW Minimum Clock Pulse Width 15 ns tS Minimum Setup Time Data to Clock 5 ns tH Minimum Hold Time Clock to Data 12 ns Symbol Parameter Conditions TA 25q TA 40 to 85qCTA 55 to 125qC Units Typ Guaranteed Limits tPHL Maximum Propagation CL 50 pF 18 30 38 45 ns tPLH Delay Data to Output tPHL Maximum Propagation Delay CL 50 pF 17 30 44 53 ns tPLH Latch Enable to Output tPZH Maximum Enable Propagation CL 50 pF 22 30 38 45 ns tPZL Delay Control to Output RL 1 k: tPHZ Maximum Disable Propagation CL 50 pF 15 30 38 45 ns tPLZ Delay Control to Output RL 1 k: tTHL Maximum Output CL 50 pF 6 12 15 18 ns tTLH Rise and Fall Time tW Minimum Clock Pulse Width 15 20 24 ns tS Minimum Setup Time Data to Clock 35 6 8 ns tH Minimum Hold Time Clock to Data 4 12 15 18 ns CIN Maximum Input Capacitance 10 10 10 pF COUT Maximum Output Capacitance 20 20 20 pF CPD Power Dissipation Capacitance OC VCC 5pF (Note 5) OC GND 52 |
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