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PCD3316 Datasheet(PDF) 11 Page - NXP Semiconductors |
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PCD3316 Datasheet(HTML) 11 Page - NXP Semiconductors |
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11 / 30 page  Philips Semiconductors PCD3316 CIDCW receiver Product specification 11 March 1999 11 of 30 9397 750 04824 © Philips Electronics N.V. 1999. All rights reserved. 7.12.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a STOP condition (P); see Figure 10. 7.12.3 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal; see Figure 11. 7.12.4 Acknowledge The number of data bytes transferred between the START and the STOP conditions from the transmitter to the receiver is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge-related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. Fig 9. I2C-bus configuration. MBA605 MASTER TRANSMITTER / RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER / RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER / RECEIVER SDA SCL Fig 10. START and STOP conditions for the I2C-bus. MBA608 SDA SCL P STOP condition SDA SCL S START condition Fig 11. I2C-bus bit transfer. MBA607 data line stable; data valid change of data allowed SDA SCL |
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