W39F010

Publication Release Date: December 26, 2005

- 7 -

Revision A4

6.

FUNCTIONAL DESCRIPTION

6.1

Device Bus Operation

6.1.1

Read Mode

The read operation of the W39F010 is controlled by #CE and #OE, both of which have to be low for

the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip

is de-selected and only standby power will be consumed. #OE is the output control and is used to gate

data from the output pins. The data bus is in high impedance state when either #CE or #OE is high.

Refer to the timing waveforms for further details.

6.1.2

Write Mode

Device erasure and programming are accomplished via the command register. The contents of the

register serve as inputs to the internal state machine. The state machine outputs dictate the function

of the device.

The command register itself does not occupy any addressable memory location. The register is a latch

used to store the commands, along with the address and data information needed to execute the

command. The command register is written to bring #WE to logic low state, while #CE is at logic low

state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE,

whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens

first. Standard microprocessor write timings are used.

Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing

parameters.

6.1.3

Standby Mode

There are two ways to implement the standby mode on the W39F010 device, both using the #CE pin.

A CMOS standby mode is achieved with the

±0.5V. Under this condition the current

is typically reduced to less than 50

Under this condition the current is typically reduced to 2 mA.

In the standby mode the outputs are in the high impedance state, independent of the #OE input.

6.1.4

Output Disable Mode

output pins to be in a high impedance state.

6.2

Data Protection

The W39F010 is designed to offer protection against accidental erasure or programming caused by

spurious system level signals that may exist during power transitions. During power up the device

automatically resets the internal state machine in the Read mode. Also, with its control register

architecture, alteration of the memory contents only occurs after successful completion of specific

multi-bus cycle command sequences. The device also incorporates several features to prevent