W39F010

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6.4.4

Chip Erase Command

Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the

"set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase

command.

Chip erase does not require the user to program the device prior to erase. Upon executing the

Embedded Erase Algorithm command sequence the device will automatically erase and verify the

entire memory for an all one data pattern. The erase is performed sequentially on each pages at the

same time (see "Feature"). The system is not required to provide any controls or timings during these

operations.

The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and

terminates when the data on DQ7 is "1" at which time the device returns to read the mode.

Refer to the Erase Command Flow Chart using typical command strings and bus operations.

6.4.5

Page Erase Command

Page erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the

"set-up" command. Two more "unlock" write cycles then follows by the page erase command. The

page address (any address location within the desired page) is latched on the falling edge of #WE,

while the command (50H) is latched on the rising edge of #WE.

Page erase does not require the user to program the device prior to erase. When erasing a page, the

remaining unselected pages are not affected. The system is not required to provide any controls or

timings during these operations.

The automatic page erase begins after the erase command is completed, right from the rising edge of

the #WE pulse for the last page erase command pulse and terminates when the data on DQ7, Data

Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an

address within any of the pages being erased.

Refer to the Erase Command flow Chart using typical command strings and bus operations.

6.5

Write Operation Status

6.5.1

DQ7: Data Polling

The W39F010 device features Data Polling as a method to indicate to the host that the embedded

algorithms are in progress or completed.

During the Embedded Program Algorithm, an attempt to read the device will produce the complement

of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to

read the device will produce the true data last written to DQ7.

During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7

output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce

a "1" at the DQ7 output.

For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write

pulse sequences. For page erase, the Data Polling is valid after the last rising edge of the page erase

#WE pulse. Data Polling must be performed at addresses within any of the pages being erased.

Otherwise, the status may not be valid.