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PCD4440T Datasheet(PDF) 9 Page - NXP Semiconductors |
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PCD4440T Datasheet(HTML) 9 Page - NXP Semiconductors |
9 / 20 page 1996 Dec 20 9 Philips Semiconductors Product specification Analog voice scrambler/descrambler PCD4440T 8I2C BUS INTERFACE The I2C-bus is for two-way communication between different ICs or modules. It uses only two lines, a serial data line (SDA) and a serial clock line (SCL), both of which are bi-directional. Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 8.1 Bit transfer (see Fig.6) One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals. 8.2 Start and stop conditions (see Fig.7) Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). Fig.6 Bit transfer. MBC621 data line stable; data valid change of data allowed SDA SCL Fig.7 Start and stop conditions. MBC622 SDA SCL P STOP condition SDA SCL S START condition |
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